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參數(shù)資料
| 型號(hào)： | VG36128161BT-7H |
| 廠商： | VANGUARD INTERNATIONAL SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁(yè)數(shù)： | 5/69頁(yè) |
| 文件大?。?/td> | 1335K |
| 代理商： | VG36128161BT-7H |
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Document :1G5-0183
Rev.5
Page 13
VIS
VG36128401B / VG36128801B / VG36128161B
CMOS Synchronous Dynamic RAM
(3/3)
Current
CS
RAS
CAS
WE
Address
Command
Action
Notes
Write
recovering
H
X
DESL
Nop
Enter row active after tDPL
L
H
X
NOP
Nop
Enter row active after tDPL
L
H
L
X
BST
Nop
Enter row active after tDPL
L
H
L
H
BA, CA, A10
READ/READA
Start read, Determine AP
8
L
H
L
BA, CA, A10
WRIT/WRITA
New write, Determine AP
L
H
BA, RA
ACT
ILLEGAL
3
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
H
X
PEF/SELF
ILLEGAL
L
Op - Code
MRS
ILLEGAL
Write
recovering
with auto
precharge
H
X
DESL
Nop
Enter precharge after tDPL
L
H
X
NOP
Nop
Enter precharge after tDPL
L
H
L
X
BST
Nop
Enter precharge after tDPL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
3,8,11
L
H
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
3,11
L
H
BA, RA
ACT
ILLEGAL
3,11
L
H
L
BA, A10
PRE/PALL
ILLEGAL
3
L
H
X
REF/SELF
ILLEGAL
L
Op - Code
MRS
ILLEGAL
Auto
Refreshing
H
X
DESL
Nop Enter idle after tRC
L
H
X
NOP/BST
Nop Enter idle after tRC
L
H
L
X
READ/WRIT
ILLEGAL
L
H
X
ACT/PRE/PALL
ILLEGAL
L
X
REF/SELF/MRS ILLEGAL
Mode regis-
ter
setting
H
X
DESL
Nop
Enter idle after 2 Clocks
L
H
X
NOP
Nop
Enter idle after 2 Clocks
L
H
L
X
BST
ILLEGAL
L
H
L
X
READ/WRITE
ILLEGAL
L
X
ACT/PRE/PALL/
REF/SELF/MRS
ILLEGAL
Note
1. All entries assume that CKE was active (High level) during the preceding clock cycle.
2. If both banks are idle, and CKE is inactive (Low level), the device will enter Power downmode.
All input buffers except CKE will be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by BankAddress(BA),
depending on the
state of that bank.
4. If both banks are idle, and CKE is inactive (Low level), the device will enter Self refresh mode.
All input buffers except CKE will be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which don
’t satisfy t
DPL.
10. Illegal if tRRD is not satisfied.
11. Illegal for single bank, but legal for other banks in multi-bank devices.
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PDF描述 |
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| VG36128161BFL-7L | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VG36128401A | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
| VG36128401BT | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
| VG36128801A | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
| VG36128801BT | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
| VG3617161BT-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
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