參數(shù)資料
型號(hào): VG36128161BT-7H
廠商: VANGUARD INTERNATIONAL SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝: 0.400 INCH, PLASTIC, TSOP2-54
文件頁數(shù): 23/69頁
文件大?。?/td> 1335K
代理商: VG36128161BT-7H
Document :1G5-0183
Rev.5
Page 3
VIS
VG36128401B / VG36128801B / VG36128161B
CMOS Synchronous Dynamic RAM
Ball Descriptions
Ball Out
Pin Name
Function
Ball Out
Pin Name
Function
F2
CLK
Master Clock
F1, E8
UDQM, LDQM DQ Mask Enable
F3
CKE
Clock Enable
H7, H8, J8, J7,
J3, J2, H3, H2,
H1, G3, H9, G2
A0-11
Address Input
G9
/CS
Chip Select
G7, G8
BA0,1
Bank Address
F8
/RAS
Row Address Strobe
A9, E7, J9
VDD
Power Supply
F7
/CAS
Column Address Strobe
A7, B3, C7, D3
VDDQ
Power Supply for DQ
F9
/WE
Write Enable
A1, E3, J1
VSS
Ground
A8, B9, B8, C9,
C8, D9, D8, E9,
E1, D2, D1, C2,
C1, B2, B1, A2
DQ0 ~ DQ15
Data I/O
A3, B7, C3, D7
VSSQ
Ground for DQ
VFBGA BALL ASSIGNMENT (Top View, x16 Only)
A
B
J
H
G
F
E
D
C
1
2
3
4
5
6
7
8
9
VSS
DQ15
VSSQ
VDDQ
DQ0
VDD
DQ14
DQ13
VDDQ
VSSQ
DQ2
DQ1
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
DQ8
NC
VSS
VDD
LDQM
DQ7
UDQM
CLK
CKE
CAS#
RAS#
WE#
NC
A11
A9
BA0
BA1
CS#
A8
A7
A6
A0
A1
A10
VSS
A5
A4
A3
A2
VDD
54 Balls 10x9 mm
0.80 mm Ball Pitch
A1 Corner
相關(guān)PDF資料
PDF描述
VG36128161BFL-7L 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54
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