參數(shù)資料
型號: VG36128161BT-7H
廠商: VANGUARD INTERNATIONAL SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝: 0.400 INCH, PLASTIC, TSOP2-54
文件頁數(shù): 17/69頁
文件大?。?/td> 1335K
代理商: VG36128161BT-7H
Document :1G5-0183
Rev.5
Page 24
VIS
VG36128401B / VG36128801B / VG36128161B
CMOS Synchronous Dynamic RAM
10. BURST Termination
There are two methods to terminate a burst operation other than using a read or a write command. One is the burst
stop command and the other is the precharge command.
10.1 BURST Stop Command
During a read burst, when the burst stop command is issued, the burst read data are terminated and the data bus
goes to high-impedance after the CAS latency from the burst stop command.
During a write burst, when the burst stop command is issued, the burst write data are termained and data bus goes to
Hi-Z at the same clock with the burst stop command.
Burst Termination
Remark BST: Burst stop command
Remark BST: Burst command
Burst lengh=X, CAS Intency=2,3
CLK
Command
CAS latency=2
DQ
CAS latency=3
DQ
Q0
Q2
Q1
Read
T0
T1
T2
T3
T4
T5
T6
T7
BST
Hi-Z
Q0
Q2
Q1
Hi-Z
Burst lengh=X, CAS latency=2,3
CLK
Command
CAS latency=2,3
DQ
Q0
Q2
Q1
Write
T0
T1
T2
T3
T4
T5
T6
T7
BST
Hi-Z_
Q0
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