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參數(shù)資料
| 型號(hào)： | VG36128161BT-7H |
| 廠商： | VANGUARD INTERNATIONAL SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁(yè)數(shù)： | 10/69頁(yè) |
| 文件大?。?/td> | 1335K |
| 代理商： | VG36128161BT-7H |
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Document :1G5-0183
Rev.5
Page 18
VIS
VG36128401B / VG36128801B / VG36128161B
CMOS Synchronous Dynamic RAM
7. Precharge
The precharge command can be asserted anytime after tRAS(min.) is satisfied.
Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM enters the
idle state after tRP(min.) is satisfied. The parameter tRP is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as follows.
PrechargeE
In order to write all data to the memory cell correctly, the asynchronous parameter
”t
DPL” must be satisfied. The
tDPL(min.) specification defines the earliest time that a precharge command can be asserted. The minimum number of
clocks can be calculated by dividing tDPL(min.) with the clock cycle time.
In summary, the precharge command can be asserted relative to the reference clock that indicates the last data word is
valid. In the following table, minus means clocks before the reference; plus means time after the reference.
CAS latency
Read
Write
2
-1
+ tDPL(min.)
3
-2
+ tDPL(min.)
Burst lengh=4
CLK
Command
CAS latency = 2
DQ
Command
CAS latency = 3
DQ
(tRAS is satisfied)
Hi - Z
Q0
Q3
Q2
Q1
PRE
Q0
Q3
Q2
Q1
Read
T0
T1
T2
T3
T4
T5
T6
T7
PRE
Hi - Z
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VG36128161BFL-7L | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54 |
| VG95234E32-5P1X | 2 CONTACT(S), ALUMINUM ALLOY, MALE, MIL SERIES CONNECTOR, CLAMP AND CRIMP, PLUG |
| VG95234E32-5P1Y | 2 CONTACT(S), ALUMINUM ALLOY, MALE, MIL SERIES CONNECTOR, CLAMP AND CRIMP, PLUG |
| VG95234E32-5P1Z | 2 CONTACT(S), ALUMINUM ALLOY, MALE, MIL SERIES CONNECTOR, CLAMP AND CRIMP, PLUG |
| VG95234E32-5PN | 2 CONTACT(S), ALUMINUM ALLOY, MALE, MIL SERIES CONNECTOR, CLAMP AND CRIMP, PLUG |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VG36128401A | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
| VG36128401BT | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
| VG36128801A | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
| VG36128801BT | 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM |
| VG3617161BT-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
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