參數(shù)資料
型號(hào): VG36128161BT-7H
廠商: VANGUARD INTERNATIONAL SEMICONDUCTOR CORP
元件分類: DRAM
英文描述: 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝: 0.400 INCH, PLASTIC, TSOP2-54
文件頁(yè)數(shù): 14/69頁(yè)
文件大?。?/td> 1335K
代理商: VG36128161BT-7H
Document :1G5-0183
Rev.5
Page 21
VIS
VG36128401B / VG36128801B / VG36128161B
CMOS Synchronous Dynamic RAM
9. Read / Write Command Interval
9.1 Read to Read Command Interval
During a read cycle when a new read command is asserted, it will be effective after the CAS latency, even if the previ-
ous read operation has not completed. READ will be interrupted by another READ.
Each read command can be asserted in every clock without any restriction.
Burst lengh=4, CAS latency=2
CLK
Command
DQ
QA0
QB2
QB1
QB0
Read A
T0
T1
T2
T3
T4
T5
T6
T7
Hi-Z_
T8
1 cycle
QB3
Read B
Burst lengh=4, CAS latency=2
CLK
Command
DQ
QA0
QB2
QB1
QB0
Write A
T0
T1
T2
T3
T4
T5
T6
T7
Hi-Z_
T8
1 cycle
QB3
Write B
WRITE to WRITE Command Interval
9.2 Write to Write Command Interval
During a write cycle, when a new Write command is asserted, the previous burst will terminated and the new burst will
begin with a new write command. WRITE will be interrupted by another WRITE.
Each write command can be asserted in every clock without any restriction.
READ to READ Command Interval
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VG36128161BFL-7L 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA54
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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VG36128401BT 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM
VG36128801A 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM
VG36128801BT 制造商:VML 制造商全稱:VML 功能描述:CMOS Synchronous Dynamic RAM
VG3617161BT-10 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM