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參數(shù)資料
| 型號： | VES1820X |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Single chip DVB-C channel receiver(單片DVB-C頻道接收器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | MQFP-100 |
| 文件頁數(shù)： | 9/40頁 |
| 文件大小： | 182K |
| 代理商： | VES1820X |
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1999 March 01
9
Philips Semiconductors
Product specification
Single chip DVB-C channel receiver
VES1820X
SYMBOL
CMCAP
PIN NUMBER
85
TYPE
I
DESCRIPTION
This pin is connected to a tap point on an internal resistor divider
used to create CMO and CMI. An external capacitor of value 0.1
μ
f
should be connected between this point and ground to provide good
power supply rejection from the positive supply at higher
frequencies.
An external resistor of value 3.3k should be connected between
this pin and ground to provide good accurate bias currents for the
analog circuits on the ADC.
This is the output of an on-chip resistor divider. An external capacitor
of value 0.1
μ
f should be connected between this point and ground to
provide good power supply rejection from the positive supply at
higher frequencies. Reference voltages VREFP and VREFM are
derived from the voltage on VREF.
This is a positive voltage reference for the A/D converter. It is derived
from the voltage on pin VREF through an on-chip fully-differential
amplifier. The voltage on this pin is nominally equal to CMO + 0.25
volts.
This is the negative voltage reference for the A/D converter. It is
derived from the voltage on pin VREF through an on-chip fully-
differential amplifier. The voltage on this pin is nominally equal to
CMO- 0.25 volts.
This pin provides the common-mode out voltage for the analog
circuits on the ADC. It is the buffered version of a voltage derived
from an on-chip resistor devider, and has a nominal value of 0.5 x
VD3.
This pin provides the common-mode in voltage for the analog circuits
on the ADC. It is the buffered version of a voltage derived from an
on-chip resistor devider, and has a nominal value of 0.75 x VD3.
Power supply input for the digital switching circuitry (3.3 typ).
Ground return for the digital switching circuitry.
Power supply input for the analog clock drivers (3.3V typ).
Ground return for the analog clock drivers.
Power supply input for the analog circuits (3.3V typ).
Ground return for analog circuits.
Power supply input that connects to an n-well guard ring that
surrounds the ADC (3.3V typ).
3.3V supply for the digital section of the PLL.
Ground connection for the digital section of the PLL.
Ground connection for the analog section of the PLL.
3.3V supply for the analog section of the PLL.
P-well bias for the analog section of the PLL. Must be tied to 0V.
RBIAS
82
I
VREF
88
O
VREFP
87
O
VREFM
86
O
CMO
84
O
CMI
83
O
VD1
VS1
VD2
VS2
VD3
VS3
VD4
81
80
94
93
89
90
95
I
I
I
I
I
I
I
DVCC
DGND
PLLGND
PLLVCC
PPLUS
96
97
98
99
100
I
I
I
I
I
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