參數(shù)資料
型號(hào)： VES1820X
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Single chip DVB-C channel receiver(單片DVB-C頻道接收器)
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： MQFP-100
文件頁數(shù)： 26/40頁
文件大?。?/td> 182K
代理商： VES1820X
1999 March 01
26
Philips Semiconductors
Product specification
Single chip DVB-C channel receiver
VES1820X
DESCI
DESCrambler Inhibition parameter. When set high, DESCI inhibits the
descrambling process within the VES1820X. The default value is DESCI = 0
which means "descrambler validated ".
RSI
Reed Solomon Inhibition parameter. When set high, RSI inhibits the correction
procedure of the RS decoder within the VES1820X. The MSB of the second byte
(error indicator) is not set high even if the provided packet is uncorrectable. The
default value is RSI = 0 which means "correction capability of RS decoder
validated ".
C[1:0]
C[1:0] sets the two parameters (
α
,
β
) used in the synchronization block. In the
frame acquisition phase,
α
defines the number of consecutive MPEG2 sync (or
sync
) that the VES1820X must find to declare the deinterleaver synchronized and
to switch to the tracking phase.
In the tracking phase,
β
defines the number of consecutive MPEG2 sync (or
sync
)
that the VES1820X must miss to declare the deinterleaver desynchronized and to
switch back to the sync phase.The default value is C[1:0] = 3
16
which
corresponds to
α
= 6 and
β
= 15.
C[1]
0
0
1
1
C[0]
0
1
0
1
α
5
5
6
6
β
6
8
10
15
CLB_UNC
CLBUNC is an active low reset signal which clears the 7-bit counter used to
memorize the number of uncorrectable packets contained in register
CPT_UNCOR. To clear the counter first write CLB_UNC=0 then CLB_UNC=1
(default).
PVBER[1/0]
These two bits allow to program the number of bits of the sequence length where
the demodulator output Bit Error Rate is computed. The number of bits varies from
10
5
to 10
8
bits. The default value is PVBER = 1
16
which corresponds to 10
6
bits.
PVBER[1]
0
0
1
1
PVBER[0]
0
1
0
1
Number of bits
10
10
10
10
5
6
7
8
18. SYNC
11
16
READ ONLY
EQ_ALGO indicates whether the current algorithm used for equalization is the
acquisition one (EQ_ALGO=0) or the tracking one (EQ_ALGO=1).
EQ_ALGO
CARLOCK
CARLOCK goes high when the demodulator part within the VES1820X is
synchronized : carrier has been recovered, else CARLOCK is low.
FSYNC
FSYNC goes high when the deinterleaver within the VES1820X is synchronized :
α
consecutives MPEG2 sync pattern (or
sync
) have been detected. FSYNC goes
low when
β
consecutives MPEG2 sync pattern (or
sync
) have been missed.
α
and
β
are programmable within CONF register.
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