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參數(shù)資料
| 型號： | VES1820X |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Single chip DVB-C channel receiver(單片DVB-C頻道接收器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | MQFP-100 |
| 文件頁數(shù)： | 29/40頁 |
| 文件大?。?/td> | 182K |
| 代理商： | VES1820X |
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1999 March 01
29
Philips Semiconductors
Product specification
Single chip DVB-C channel receiver
VES1820X
PDOWN
When PDOWN is set high the internal ADC is in a stand-by mode (no
consumption).
When PDOWN = 0 the ADC is active.
29. EQCONF2
1C
16
READ/WRITE
STEPTL[2 :0] STEPTL[2 :0] allow to program the step of the tap leakage algorithm that can be
used in the adaptation process. Default is 000 and means that tap leakage is not
used.
CTADAPT
CTADAPT is used only if the equalizer is inhibited. In this case, it indicates if the
center tap coefficient of the equalizer is adapted (CTADAPT=1) or not
(CTADAPT=0). It can then compensate for eventual AGC residual error.
CTPHASE
CTPHASE indicates if the imaginary part of the center tap coefficient is adapted
(CTPHASE=1,default) or not (CTPHASE=0).
SGNALGO SGNALGO selects between 2 options in the adaptation algorithm. If DFE mode is
selected then SGNALGO must be set to 1.
30. CKOFFSET
1D
16
READ
CKOFF[7 :0] CKOFF[7 :0] provides the symbol clock frequency offset (SRoffset) according to
the following formula :
If DYN=0 SRoffset = (CKOFF * 120 / 128) ppm
If DYN=1 SRoffset = (CKOFF * 240 / 128) ppm
31. PLL
1E
16
READ/WRITE
DIVSEL[2 :0] DIVSEL[2 :0] allow to set the multiplying factor of the PLL so that the system clock
(2*SACLK) is equal to XIN*(DIVSEL+1) (DIVSEL from 0 to 7). Default is
DIVSEL=000.
PDPLL
When PDPLL=1 (default) the PLL is in reset/power-down mode, else the PLL is
active.
BYPPLL
When BYPPLL=1 (default) the PLL is bypassed, else the PLL is used.
OOLCLRN When set high OOLCLRN enables Out Of Lock detection of the PLL. When set low
it clears the Out Of Lock flag (OOLN) and resets the OOL circuitry.
OOLN
Read only flag, indicating if the PLL is out of lock (OOLN=0).
32. INTSEL
20
16
READ/WRITE
When SERINT=0, then the output interface is a parallel interface on pins DO[7:0] as
described in
FIGURE 6 and FIGURE 7 page 13
.
When SERINT=1, then the output interface is a serial interface on pin DO[0], as
described in
FIGURE 8 page 14
.
SERINT
MSBFIRST If SERINT=1, MSBFIRST determines if the output bytes are serialized MSB first
(MSBFIRST=1, default) or LSB first (MSBFIRST=0).
If SERINT=0, it determines if the MSB of the output byte DO[7 :0] is DO[7]
(MSBFIRST=1, default) or DO[0] (MSBFIRST=0).
SWAP
This parameter allows to swap the output pins UNCOR and PSYNC. When SWAP
= 0 default, UNCOR is on pin 42 and PSYNC on pin 43. When SWAP = 1, UNCOR
is on pin 43 and PSYNC on pin 42.
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