參數(shù)資料
型號(hào)： VES1820X
廠商： NXP SEMICONDUCTORS
元件分類(lèi)： 消費(fèi)家電
英文描述： Single chip DVB-C channel receiver(單片DVB-C頻道接收器)
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： MQFP-100
文件頁(yè)數(shù)： 31/40頁(yè)
文件大?。?/td> 182K
代理商： VES1820X
1999 March 01
31
Philips Semiconductors
Product specification
Single chip DVB-C channel receiver
VES1820X
SDEC3[7:0]
SDEC3 represents the number of saturations that occur at the output of third
decimation filter, during a period of 2048, 4096, 8192 or 16384 samples, depending
on the value programmed on parameter SSAT [1:0].
39. SATAAF
27
16
READ ONLY
SAAF represents the number of saturations that occur at the output of the anti-
aliasing filter, during a period of 2048, 4096, 8192 or 16384 samples, depending on
the value programmed on parameter SSAT [1:0].
SAAF[7:0]
40. SATTHR
30
16
READ/WRITE
STHR is a threshold value, compared to the register SATADC. If SATADC >
STHR then an interrupt can be generated on pin IT. (See register ITSEL).
STHR[7:0]
41. HALFTHR
31
16
READ/WRITE
HLFTHR is a threshold value, compared to the register HLFADC.
If HLFADC < HLFTHR then an interrupt can be generated on pin IT (See register
ITSEL).
HLFTHR[7:0]
42. ITSEL
32
H
READ/WRITE
INTerrupt Enable. When ITEN is set to 1 then the output pin IT is configured as an
interrupt pin. The event(s) that will produce an interrupt is defined by ITSEL[6:0].
When ITEN is set to 0, the output pin IT is a control line output, which value is
determined by ITSEL[6].
If ITSEL[0] is set to 1, then an interrupt is generated on each rising edge of frame
synchronization flag. (not synchronized ----> synchronized).
ITEN
ITSEL[0]
ITSEL[1]
If ITSEL[1] is set to 1, then an interrupt is generated on each falling edge of frame
synchronization flag. (synchronized ----> not synchronized).
ITSEL[2]
If ITSEL[2] is set to 1, then an interrupt is generated on each uncorrectable
packet.
If ITSEL[3] is set to 1, then an interrupt is generated each time the VBER is
refreshed. So there will be an interrupt each 10
bits depending on the value programmed in parameter PVBER (register RSCONF,
index 10
16
).
ITSEL[3]
5
, 10
6
, 10
7
or 10
8
demodulator output
ITSEL[4]
If ITSEL[4] is set to 1, then an interrupt is generated each time the value of register
SATADC (index 22
16
) is greater than the threshold SATTHR (index 30
16
).
ITSEL[5]
If ITSEL[5] is set to 1, then an interrupt is generated each time the value of register
HALFADC (index 23
16
) is less than the threshold HALFTHR (index 31
16
).
ITSEL[6]
If ITSEL[6] is set to 1, then an interrupt is generated each time the AGC is saturated
(AGC = 0 or ACG = 255).
43. ITSTAT
33
16
READ ONLY
is the interrupt status register. Each time the microcontroller detects an interrupt on
pin IT, it can read out this register to know which event among those selected by
ITSEL[6:0] has produced the interrupt (ITSTAT(i) corresponds to ITSEL(i)). This
register is automatically cleared after each reading.
ITSTAT[6:0]
44. PWMREF
34
16
READ/WRITE
is the value that will be PWM encoded and output on pin FEL when parameter
FELPWM of register AGCCONF (index 02
16
) is set to 1.
PWMR[7:0]
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