參數(shù)資料
型號(hào): VES1820X
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: Single chip DVB-C channel receiver(單片DVB-C頻道接收器)
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: MQFP-100
文件頁(yè)數(shù): 28/40頁(yè)
文件大小: 182K
代理商: VES1820X
1999 March 01
28
Philips Semiconductors
Product specification
Single chip DVB-C channel receiver
VES1820X
POINT
Programmable Output INTerface.
POINT = 1 (default) allows to not provide the check bytes of the RS decoder but a
low level. In that case the output clock OCLK is also fixed to a DC level depending
on POCLK.
20.CPT_UNCOR
13
16
READ ONLY
7-bit counter which memorizes the number of uncorrectable packets found after a
master reset (hard or soft) or between two CLB_UNC writing. When the counter
reaches 7F
16
, it remains in this state until either a master reset or a CLB_UNC
occurs. Note that reading the CPTU[7:0] register does not reset the counter.
CPTU[7:0] is READ ONLY.
CPTU[6:0]
21. BER_LSB
14
16
READ ONLY
8 LSB of the BER[19:0] register.
BER[7:0]
22. BER_MID
15
16
READ ONLY
8 MID bit of the BER[19:0] register.
BER[15:8]
23. BER_MSB
16
16
READ ONLY
4 MSB bit of the BER[19:0] register.
BER[19:0] indicates the contents of the 20-bit error counter used in the
demodulator output Bit Error Rate measurement. These 20 bits must be
interpreted as a decimal number that must be multiplied by 10
depending on the programmable value of PVBER, to directly obtain the BER at
demodulator output. For instance, if PVBER = 11 (in register RSCONF) and
VBER[19:0] =25
OUTPUT SIGNAL QUALITY MEASUREMENT (BER) on page 36). Reading of
BER[19:0] must occur in the following order : BER_LSB, BER_MID, BER_MSB.
BER[19:16]
-5
,
10
-6
10
-7
or 10
-8
, then the BER at demodulator output is 2.5 X 10
-7
. (See
24.VAGC
17
16
READ ONLY
8 bits data output in binary format for AGC information. 00
16
corresponds to the
minimum expected gain value, and FF
16
to the maximum.
VAGC[7:0]
25. MSE
18
16
READ ONLY
MSE[7:0] represents the Mean Square Error of the demodulated output signal.
MSE[7:0] can be used as a representation of the signal quality.
MSE[7:0]
26. VAFC
19
16
READ ONLY
VAFC[7:0] indicates the frequency offset F (in 2's complement) between the
transmitter and the receiver, when the carrier has been recovered.
F = (VAFC x RS) / 1024 . RS is the Symbol Rate.
VAFC [7:0]
27. IDENTITY
1A
16
READ ONLY
contains the value 7B
16
which corresponds to revision 1 of the VES1820X.
IDENTITY
28.ADC
1B
16
READ/WRITE
PCLK sets the polarity of internal sampling clock. When an external ADC is used
PCLK must be set to 0 default (sampling on rising edge of SACLK). When the
internal ADC is used PCLK must be set to 1 (sampling on falling edge of SACLK).
PCLK
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