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參數(shù)資料
| 型號： | VES1820X |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Single chip DVB-C channel receiver(單片DVB-C頻道接收器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | MQFP-100 |
| 文件頁數(shù)： | 13/40頁 |
| 文件大?。?/td> | 182K |
| 代理商： | VES1820X |
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1999 March 01
13
Philips Semiconductors
Product specification
Single chip DVB-C channel receiver
VES1820X
FIGURE 6 : PARALLEL OUTPUT INTERFACE MODE A
Notes :
- OCLK is a jittered clock which average frequency is N*SymbolRate/8, where N is the spectral
efficiency of the modulation. The polarity of OCLK is programmable.
- DEN is active high (if PDEN=0) only during the 188 bytes of a packet
- PSYNC is active high (if PPSYNC=0) only during the sync byte (47H)
FIGURE 7 : PARALLEL OUTPUT INTERFACE MODE B
Notes :
- OCLK is a division of the sampling clock by a programmable factor from 1 to 16. So it is a regular
clock which frequency must be greater than N*SymbolRate/8, where N is the spectral efficiency of
the modulation. The polarity of OCLK is programmable.
- DEN is active high (if PDEN=0) only during the valid bytes
- PSYNC is active high (if PPSYNC=0) only during the sync byte (47H)
47H
D1
D187
D2
47H
OCLK
DO(7:0)
DEN
PSYNC
UNCOR
47H
D1
D187
D2
47H
OCLK
DO(7:0)
DEN
PSYNC
UNCOR
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