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參數(shù)資料
| 型號： | VES1820X |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Single chip DVB-C channel receiver(單片DVB-C頻道接收器) |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | MQFP-100 |
| 文件頁數(shù)： | 27/40頁 |
| 文件大?。?/td> | 182K |
| 代理商： | VES1820X |
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1999 March 01
27
Philips Semiconductors
Product specification
Single chip DVB-C channel receiver
VES1820X
FEL
Front End Lock. FEL goes high when the 2 signals CARLOCK and FSYNC are
both at a high level : VES1820X is synchronized according to the DVB
specifications.
BER[1:0]
BER[1:0] gives a rough idea of the Bit Error Rate at the demodulator output
BER[1:0] determines 4 areas of BER as shown in the following table :
BER
> 10
BER[1]
0
0
1
1
BER[0]
0
1
0
1
-2
10
10
-3
< BER < 10
-4
< BER < 10
< 10
-3
-3
-4
NODVB
When high this means that the deinterleaver has been able to synchronize in DVB
mode but the framing is not DVB compliant (there is no
sync
byte every 8
frames).
19. POLA
12
16
READ/WRITE
Determines if the VES1820X output clock OCLK is inverted or not. When POCLK
is set low (default), the OCLK clock is not inverted, and the falling edge of the
clock is located in the middle of the provided DO[7:0] byte. When POCLK is set
high, then the rising edge of the clock is located in the middle of the DO[7:0]
output byte.
POCLK
PDEN
Determines if the VES1820X output signal DEN is inverted or not before being
provided. When set low (default), DEN is not inverted and therefore is high during
the 188 first bytes of each packet and low for the 16 remaining bytes. When set
high DEN is low for 188 bytes and high for 16.
PUNCOR
Determines if the VES1820X output signal UNCOR is inverted or not before being
provided. When set low (default), UNCOR is not inverted and therefore is high
during the 188 first bytes of each packet and low for the 16 remaining bytes only
in case where the provided packet is declared uncorrectable by the RS decoder. If
the packet is correctable UNCOR remains low for the 204 bytes. When set high,
UNCOR is low for 188 bytes and high for 16, always in case of an uncorrectable
packet. If the packet is correctable UNCOR remains high for the 204 bytes of the
packet.
PPSYNC
Determines if the VES1820X output signal PSYNC is inverted or not before being
provided. When set low (default), PSYNC output signal is not inverted and
therefore is high during the first byte of each packet (sync byte 47
16
and low for
the 203 remaining bytes. When set high, PSYNC is low for the first byte of each
packet (sync byte 47
16
) and high for 203 remaining bytes.
PFEL
Determines if the VES1820X output signal FEL is inverted or not before being
provided. When set low (default) FEL is not inverted and is high when the
VES1820X is fully synchronized. When set high, FEL is inverted and is low when
the VES1820X is fully synchronized.
P/MF
Determines whether the PSYNC or MFSTART signal is provided on the PSYNC
output pin of the VES1820X. When set high (default), PSYNC is provided. When
set low, MFSTART is provided. MFSTART corresponds to the detection of the
inverted sync byte B8
16
: MFSTART is high one frame out of eight for a period of
OCLK at the beginning of the packet.
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