- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄297706 > V58C2128804-75L (MOSEL-VITELIC) 16M X 8 DDR DRAM, 0.75 ns, PDSO66 PDF資料下載
參數(shù)資料
| 型號： | V58C2128804-75L |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 16M X 8 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | PLASTIC, TSOP2-66 |
| 文件頁數(shù)： | 42/58頁 |
| 文件大?。?/td> | 722K |
| 代理商： | V58C2128804-75L |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁當(dāng)前第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁
47
MOSEL VITELIC
V58C2128(804/404/164)SAT
V58C2128(804/404/164)SAT Rev. 1.1 February 2001
Figure 38 - INITIALIZE AND MODE REGISTER SETS
CKE
LVCMOS LOW LEVEL
DQ
BA0, BA1
200 cycles of CLK**
Extended
Mode
Register
Set
Load
Mode
Register,
Reset DLL
(with A8 = H)
Load
Mode
Register
(with A8 = L)
tMRD
tRP
tRFC
t IS
Power-up:
VDD and
CLK stable
T = 200
s
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
High-Z
tIH
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
DM
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
DQS
High-Z
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
A0-A9, A11
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
A10
ALL BANKS
DON'T CARE
CK
/CK
tCK
tCH
tCL
VTT
(system*)
t VTD
VREF
VDD
VDDQ
COMMAND
MRS
NOP
PRE
EMRS
AR
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
AR
tIS tIH
BA0=H,
BA1=L
tIS tIH
BA0=L,
BA1=L
tIS tIH
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
CODE
tIS tIH
CODE
MRS
BA0=L,
BA1=L
CODE
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
PRE
ALL BANKS
tIS tIH
RA
ACT
BA
* = VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latch-up.
** = tMRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can be applied.
The two Auto Refresh commands may be moved to follow the first MRS, but precede the second PRECHARGE ALL command.
(
)
(
)
(
)
(
)
CODE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| V58C2256324SAH-40 | 8M X 32 DDR DRAM, 0.6 ns, PBGA144 |
| V59C1512404QBLF3I | 128M X 4 DDR DRAM, 0.45 ns, PBGA60 |
| V5A010CB3H | SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 0.6A, 125VDC, 4.4mm, PANEL MOUNT |
| V5B010FB3 | SNAP ACTING/LIMIT SWITCH, SPDT, MOMENTARY, 2.3mm, PANEL MOUNT |
| V5B030CB3H | SNAP ACTING/LIMIT SWITCH, SPST, MOMENTARY, 0.6A, 125VDC, 4.4mm, PANEL MOUNT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| V58C2128804S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM |
| V58C2256 | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM |
| V58C2256164S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM |
| V58C2256324SAB30 | 制造商:Marvell 功能描述:Marvell V58C2256324SAB30 |
| V58C2256324SAB33 | 制造商:Marvell 功能描述:Marvell V58C2256324SAB33 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。