參數(shù)資料
型號： V58C2128804-75L
廠商： MOSEL-VITELIC
元件分類： DRAM
英文描述： 16M X 8 DDR DRAM, 0.75 ns, PDSO66
封裝： PLASTIC, TSOP2-66
文件頁數(shù)： 41/58頁
文件大?。?/td> 722K
代理商： V58C2128804-75L
46
V58C2128(804/404/164)SAT Rev. 1.1 February 2001
MOSEL VITELIC
V58C2128(804/404/164)SAT
Figure 36 - DATA INPUT (WRITE) TIMING
DI n = Data In for column n
Burst Length = 4 in the case shown
3 subsequent elements of Data In are applied in the programmed
order following DI n
Figure 37 - DATA OUTPUT (READ) TIMING
1. tDQSQ max occurs when DQS is the earliest among DQS and DQ signals to transition.
2. tDQSQ min occurs when DQS is the latest among DQS and DQ signals to transition.
3. tDQSQ nom, shown for reference, occurs when DQS transitions in the center among DQ signal transitions.
DON'T CARE
DQ
DM
DQS
DI
n
tDS
tDH
tDS
tDH
tDSL tDSH
t
min
DQSQ
t
max
DQSQ
DQ
DQS
t
min
DQSQ
t
max
DQSQ
t
nom
DQSQ
Burst Length = 4 in the case shown
tDV
DQS, DQ
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