參數(shù)資料
型號： V58C2128804-75L
廠商： MOSEL-VITELIC
元件分類： DRAM
英文描述： 16M X 8 DDR DRAM, 0.75 ns, PDSO66
封裝： PLASTIC, TSOP2-66
文件頁數(shù)： 28/58頁
文件大小： 722K
代理商： V58C2128804-75L
34
V58C2128(804/404/164)SAT Rev. 1.1 February 2001
MOSEL VITELIC
V58C2128(804/404/164)SAT
IDD Specifications and Conditions
(0°C < TA < 70°C, VDDQ=25V+ 0.2V, VDD=2.5 Ia2V)
Conditions
Version
Symbol
-7
-7.5
-8
Operating current - One bank Active-Precharge; tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz
for DDR266A & DDR266B; DQ,DM and DQS inputs changing twice per clock cycle; address and
control inputs changing once per clock cycle
IDD0
100
95
85
Operating current - One bank operation; One bank open, BL=4
IDD1
150
135
Percharge power-down standby current; All banks idle; power - down mode; CKE = <VIL(max);
tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM
IDD2P
25
23
Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min);
tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs
changing once per clock cycle; Vin = Vref for DQ,DQS and DM
IDD2F
45
40
Precharge Quiet standby current; CS# > = VIH(min); All banks idle; CKE > = VIH(min); tCK =
100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Address and other control inputs stable
with keeping >= VIH(min) or =<VIL(max); Vin = Vref for DQ ,DQS and DM
IDD2Q
35
32
Active power - down standby current; one bank active; power-down mode; CKE=< VIL (max); tCK
= 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM
IDD3P
30
25
Active standby current; CS# >= VIH(min); CKE>=VIH(min); one bank active; active - precharge;
tRC=tRASmax; tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B; DQ, DQS and DM
inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle
IDD3N
45
35
Operating current - burst read; Burst length = 2; reads; continguous burst; One bank active;
address and control inputs changing once per clock cycle; CL=2 at tCK = 100Mhz for DDR200, CL=2
at tCK = 133Mhz for DDR266A, CL=2.5 at tCK = 133Mhz for DDR266B ; 50% of data changing at every
burst; lout = 0 m A
IDD4R
160
140
Operating current - burst write; Burst length = 2; writes; continuous burst; One bank active address
and control inputs changing once per clock cycle; CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK =
133Mhz for DDR266A, CL=2.5 at tCK = 133Mhz for DDR266B ; DQ, DM and DQS inputs changing
twice per clock cycle, 50% of input data changing at every burst
IDD4W
150
120
Auto refresh current; tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A
& DDR266B at 133Mhz; distributed refresh
IDD5
200
190
Self refresh current; CKE =< 0.2V; External clock should be on; tCK = 100Mhz for DDR200, 133Mhz
for DDR266A & DDR266B
IDD6
2
Operating current - Four bank operation; Four bank interleaving with BL=4
IDD7
280
275
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