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參數(shù)資料
| 型號(hào)： | V58C2128804-75L |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 16M X 8 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | PLASTIC, TSOP2-66 |
| 文件頁數(shù)： | 20/58頁 |
| 文件大?。?/td> | 722K |
| 代理商： | V58C2128804-75L |
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27
MOSEL VITELIC
V58C2128(804/404/164)SAT
V58C2128(804/404/164)SAT Rev. 1.1 February 2001
TRUTH TABLE 2 – CKE
(Notes: 1-4)
NOTE:
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. DESELECT or NOP commands should be issued on any clock edges occurring during the tXSR period.
A minimum of 200 clock cycles is needed before applying a read command, for the DLL to lock.
CKEn-1 CKEn
CURRENT STATE
COMMANDn
ACTIONn
NOTES
LL
Power-Down
X
Maintain Power-Down
Self Refresh
X
Maintain Self Refresh
LH
Power-Down
DESELECT or NOP
Exit Power-Down
Self Refresh
DESELECT or NOP
Exit Self Refresh
5
HL
All Banks Idle
DESELECT or NOP
Precharge Power-Down Entry
Bank(s) Active
DESELECT or NOP
Active Power-Down Entry
All Banks Idle
AUTO REFRESH
Self Refresh Entry
H
See Truth Table 3
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