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參數(shù)資料
| 型號： | V58C2128804-75L |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 16M X 8 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | PLASTIC, TSOP2-66 |
| 文件頁數(shù)： | 29/58頁 |
| 文件大小： | 722K |
| 代理商： | V58C2128804-75L |
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35
MOSEL VITELIC
V58C2128(804/404/164)SAT
V58C2128(804/404/164)SAT Rev. 1.1 February 2001
AC Operating Conditions & Timming Specification
AC Operating Conditions
Note:
1.Vih(max) = 4.2V. The overshoot voltage duration is < 3ns at VDD.
2. Vil(min) = -1.5V. The undershoot voltage duration is < 3ns at VSS.
3. VID is the magnitude of the difference between the input level on CK and the input on CK.
4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
ELECTRICAL CHARACTERISTICS AND AC TIMING for PC266/PC200 -Absolute
Specifications
(Notes: 1-5, 14-17) (0°C < T A < 70°C; VDDQ = +2.5V ±0.2V, +2.5V ±0.2V)
Parameter/Condition
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
VREF + 0.31
V
1
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
VIL(AC)
VREF - 0.31
V
2
Input Differential Voltage, CK and CK inputs
VID(AC)
0.62
VDDQ+0.6
V
3
Input Crossing Point Voltage, CK and CK inputs
VIX(AC)
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
4
AC CHARACTERISTICS
-7
-75
-8
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX UNITS NOTES
Access window of DQs from CK/CK
tAC
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
30
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
30
Clock cycle time
CL = 2.5
tCK (2.5)
7
12
7.5
12
8
12
ns
52
CL = 2
tCK (2)
7.5
12
10
12
10
12
ns
52
DQ and DM input hold time relative to DQS
tDH
0.5
0.6
ns
26,31
DQ and DM input setup time relative to DQS
tDS
0.5
0.6
ns
26,31
DQ and DM input pulse width (for each input)
tDIPW
1.75
2
ns
31
Access window of DQS from CK/CK
tDQSCK
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
DQS input high pulse width
tDQSH
0.35
tCK
DQS input low pulse width
tDQSL
0.35
tCK
DQS-DQ skew, DQS to last DQ valid,
per group, per access
tDQSQ
0.5
0.6
ns
25,26
DQS-DQ skew, first DQS to last DQ valid,
per access
tDQSQA
0.7
0.8
ns
36
Write command to first DQS latching transition
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CK rising - setup time
tDSS
0.2
tCK
DQS falling edge from CK rising - hold time
tDSH
0.2
tCK
Half clock period
tHP
tCH, tCL
ns
34
Data-out high-impedance window from CK/CK
tHZ
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
18
Data-out low-impedance window from CK/CK
tLZ
-0.75
+0.75
-0.75
+0.75
-0.8
+0.8
ns
18
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