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參數資料
| 型號： | V58C2128804-75L |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 16M X 8 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | PLASTIC, TSOP2-66 |
| 文件頁數： | 1/58頁 |
| 文件大?。?/td> | 722K |
| 代理商： | V58C2128804-75L |
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MOSEL VITELIC
1
V58C2128(804/404/164)SAT
HIGH PERFORMANCE
2.5 VOLT 128 Mbit DDR SDRAM
4 BANKS X 4Mbit X 8 (804)
4 BANKS X 2Mbit X 16 (404)
4 BANKS X 8Mbit X 4 (164)
PRELIMINARY
V58C2128(804/404/164)SAT Rev. 1.1 February 2001
775
8
DDR266A
DDR266B
DDR200
Clock Cycle Time (tCK2)
7.5 ns
10 ns
Clock Cycle Time (tCK2.5)
7 ns
7.5 ns
8 ns
System Frequency (fCK max)
143 MHz
133 MHz
125 MHz
Features
s High speed data transfer rates with system
frequency up to 143 MHz
s Data Mask for Write Control
s Four Banks controlled by BA0 & BA1
s Programmable CAS Latency: 2, 2.5
s Programmable Wrap Sequence: Sequential
or Interleave
s Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
s Automatic and Controlled Precharge Command
s Power Down Mode
s Auto Refresh and Self Refresh
s Refresh Interval: 4096 cycles/64 ms
s Available in 66-pin 400 mil TSOP
s SSTL-2 Compatible I/Os
s Double Data Rate (DDR)
s Bidirectional Data Strobe (DQS) for input and
output data, active on both edges
s On-Chip DLL aligns DQ and DQs transitions with
CK transitions
s Differential clock inputs CK and CK
s Power Supply 2.5V ± 0.2V
s QFC options for FET control. x4 parts.
*Note: DDR 266A Supports PC2100 module with 2-2-2 timing
DDR 266B Supports PC2100 module with 2.5-3-3 timing
DDR 200 Supports PC1600 module with 2-2-2 timing
Description
The V58C2128(804/404/164)SAT is a four bank
DDR DRAM organized as 4 banks x 4Mbit x 8 (804),
4 banks x 2Mbit x 16 (404), or 4 banks x 8Mbit x 4
(164). The V58C2128(804/404/164)SAT achieves
high speed data transfer rates by employing a chip
architecture that prefetches multiple bits and then
synchronizes the output data to a system clock.
All of the control, address, circuits are synchro-
nized with the positive edge of an externally sup-
plied clock. I/O transactions are ocurring on both
edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with standard
DRAMs. A sequential and gapless data rate is pos-
sible depending on burst length, CAS latency and
speed grade of the device.
Device Usage Chart
Operating
Temperature
Range
Package Outline
CK Cycle Time (ns)
Power
Temperature
Mark
JEDEC 66 TSOP II
-7
-75
-8
Std.
L
0°C to 70°C
Blank
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相關代理商/技術參數 |
參數描述 |
|---|---|
| V58C2128804S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 128 Mbit DDR SDRAM |
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| V58C2256164S | 制造商:MOSEL 制造商全稱:MOSEL 功能描述:HIGH PERFORMANCE 2.5 VOLT 256 Mbit DDR SDRAM |
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| V58C2256324SAB33 | 制造商:Marvell 功能描述:Marvell V58C2256324SAB33 |
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