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參數(shù)資料
| 型號(hào)： | V58C2128804-75L |
| 廠商： | MOSEL-VITELIC |
| 元件分類： | DRAM |
| 英文描述： | 16M X 8 DDR DRAM, 0.75 ns, PDSO66 |
| 封裝： | PLASTIC, TSOP2-66 |
| 文件頁數(shù)： | 13/58頁 |
| 文件大?。?/td> | 722K |
| 代理商： | V58C2128804-75L |
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V58C2128(804/404/164)SAT Rev. 1.1 February 2001
MOSEL VITELIC
V58C2128(804/404/164)SAT
Precharge Timing During Write Operation
Precharge timing for Write operations in DRAMs requires enough time to satisfy the write recovery require-
ment. This is the time required by a DRAM sense amp to fully store the voltage level. For DDR SDRAMs, a
timing parameter (tWR) is used to indicate the required amount of time between the last valid write operation
and a Precharge command to the same bank.
The “write recovery” operation begins on the rising clock edge after the last DQS edge that is used to strobe
in the last valid write data. “Write recovery” is complete on the next rising clock edge that is used to strobe in
the Precharge command.
For the earliest possible Precharge command following a Write burst without interrupting the burst, the
minimum time for “write recovery” is 1.25 clock cycles. Maximum “write recovery” time is 1.75 clock cycles.
Write with Precharge Timing
(CAS Latency = Any; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
D0
D1
D2
D3
NOP
Write
NOP
PreA
NOP
CK, CK
Command
DQS
DQ
tRAS(min)
tRP(min)
BA
NOP
T9
T10
tWR
D0
D1
D2
D3
DQS
DQ
tWR
BA
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