參數(shù)資料
型號: V58C2128804-75L
廠商: MOSEL-VITELIC
元件分類: DRAM
英文描述: 16M X 8 DDR DRAM, 0.75 ns, PDSO66
封裝: PLASTIC, TSOP2-66
文件頁數(shù): 30/58頁
文件大小: 722K
代理商: V58C2128804-75L
36
V58C2128(804/404/164)SAT Rev. 1.1 February 2001
MOSEL VITELIC
V58C2128(804/404/164)SAT
Address and control input hold time
(fast slew rate)
tIH
F
.90
1.1
ns
14
Address and control input setup time
(fast slew rate)
tIS
F
.90
1.1
ns
14
Address and control input hold time
(slow slew rate)
tIH
S
1
1.1
ns
14
Address and control input setup time
(slow slew rate)
tIS
S
1
1.1
ns
14
LOAD MODE REGISTER command cycle time
tMRD
15
16
ns
DQ-DQS hold, DQS to first DQ to go non-valid,
per access
tQH
tHP
-tQHS
tHP
-tQHS
tHP
-tQHS
ns
25, 26
Data hold skew factor
tQHS
0.75
1
ns
ACTIVE to PRECHARGE command
tRAS
45
120,000
45
120,000
50
120,000
ns
35
ACTIVE to READ with Auto precharge
command
tRAP
tRAS(MIN) - (burst length * tCK/2)
ns
46
ACTIVE to ACTIVE/AUTO REFRESH
command period
tRC
60
65
70
ns
AUTO REFRESH command period
tRFC
67
75
80
ns
50
ACTIVE to READ or WRITE delay
tRCD
15
20
ns
PRECHARGE command period
tRP
15
20
ns
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
42
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
ACTIVE bank a to ACTIVE bank b command
tRRD
15
ns
DQS write preamble
tWPRE
0.25
tCK
DQS write preamble setup time
tWPRES
0
ns
20, 21
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
19
Write recovery time
tWR
15
ns
Internal WRITE to READ command delay
tWTR
1
tCK
Data valid output window
na
tQH - tDQSQ
ns
25
REFRESH to REFRESH command interval
tREFC
140.6
Average periodic refresh interval
tREFI
15.6
Terminating voltage delay to VDD
tVTD
0
ns
Exit SELF REFRESH to non-READ command
tXSNR
75
80
ns
Exit SELF REFRESH to READ command
tXSRD
200
tCK
AC CHARACTERISTICS
-7
-75
-8
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX UNITS NOTES
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