參數(shù)資料
型號: UJA1065
廠商: NXP Semiconductors N.V.
英文描述: High-speed CAN/LIN fail-safe system basis chip
中文描述: 高速的CAN / LIN故障防護系統(tǒng)基礎芯片
文件頁數(shù): 57/67頁
文件大?。?/td> 285K
代理商: UJA1065
9397 750 14409
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Objective data sheet
Rev. 01 — 10 August 2005
57 of 67
Philips Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
[1]
t
bit
= selected bit time, depends on LSC-bit; 50
μ
s or 96
μ
s (20 or 10.4 kbit/s respectively); bus load conditions (R
1
/R
2
/C
1
):
1 k
/1 k
/10 nF; 1 k
/1 k
/6.8 nF; 1 k
/open/1 nF; see
Figure 19
and
Figure 20
.
[2]
[3]
Wake-up input; pin WAKE
t
WU(ipf)
input port filter time
V
BAT42
= 5 V to 27 V
V
BAT42
= 27 V to 52 V
V3C = 11 or 10; see
Figure 14
10
50
310
-
-
-
120
250
390
μ
s
μ
s
μ
s
t
su(CS)
cyclic sense sample
setup time
Watchdog
t
WD(ETP)
earliest watchdog
trigger point
programmed Nominal
Watchdog Period (NWP);
Normal mode
programmed nominal
watchdog period; Normal
mode, Standby mode and
Sleep mode
watchdog time-out in Start-up
mode
0.45
×
NWP
-
0.55
×
NWP
t
WD(LTP)
latest watchdog
trigger point
0.9
×
NWP -
1.1
×
NWP
t
WD(init)
watchdog initializing
period
229
-
283
ms
Fail-safe mode
t
ret
retention time
Fail-safe mode; wake-up
detected
1.3
1.5
1.7
s
Reset output; pin RSTN
t
RSTN(CHT)
clamped HIGH time,
pin RSTN
clamped LOW time,
pin RSTN
interrupt monitoring
time
reset lengthening
time
RSTN driven LOW internally
but RSTN pin remains HIGH
RSTN driven HIGH internally
but RSTN pin remains LOW
INTN = 0
115
-
141
ms
t
RSTN(CLT)
229
-
283
ms
t
RSTN(INT)
229
-
283
ms
t
RSTNL
after internal or external reset
has been released; RST = 0
after internal or external reset
has been released; RST =1
0.9
-
1.1
ms
18
-
22
ms
Interrupt output; pin INTN
t
INTN
interrupt release
after SPI has read out the
Interrupt register
2
-
-
μ
s
Oscillator
f
osc
oscillator frequency
460.8
512
563.2
kHz
Table 27:
T
vj
=
40
°
C to + 150
°
C; V
BAT42
= 5.5 V to 52 V; V
BAT14
= 5.5 V to 27 V; unless otherwise specified. All voltages are defined
with respect to ground. Positive currents flow into the IC. All parameters are guaranteed over the virtual junction temperature
range by design. Products are 100 % tested at 125
°
C ambient temperature on wafer level (pre-testing). Cased products are
100 % tested at 25
°
C ambient temperature (final testing). Both pre-testing and final testing use correlated test conditions to
cover the specified temperature and power supply voltage range.
Symbol
Parameter
Conditions
Characteristics
…continued
Min
Typ
Max
Unit
D1 D3
t
bit
)
---------------------------------
=
D2 D4
t
2
t
bit
)
----------------------------------
=
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UJA1065TW 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:High-speed CAN/LIN fail-safe system basis chip
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