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參數(shù)資料
| 型號(hào)： | UJA1065 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | High-speed CAN/LIN fail-safe system basis chip |
| 中文描述： | 高速的CAN / LIN故障防護(hù)系統(tǒng)基礎(chǔ)芯片 |
| 文件頁(yè)數(shù)： | 28/67頁(yè) |
| 文件大?。?/td> | 285K |
| 代理商： | UJA1065 |
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9397 750 14409
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Objective data sheet
Rev. 01 — 10 August 2005
28 of 67
Philips Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
To protect against wrong or illegal SPI instructions, the SBC detects the following SPI
failures:
SPI clock count failure (wrong number of clock cycles during one SPI access): only
16 clock periods are allowed within one SCS cycle. Any deviation from the 16 clock
cycles results in an SPI failure interrupt, if enabled. The access is ignored by the SBC.
In Start-up and Restart mode a reset is forced instead of an interrupt
Unallowed mode changes according to
Figure 3
result in an immediate system reset
Illegal Mode register code. Undefined operating mode or watchdog period coding
results in an immediate system reset; see
Section 6.13.3
6.13.1
SPI register mapping
Any control bit which can be set by software is readable by the application. This allows
software debugging as well as control algorithms to be implemented.
Watchdog serving and mode setting is performed within the same access cycle; this only
allows an SBC mode change whilst serving the watchdog.
Each register carries 12 data bits; the other 4 bits are used for register selection and
read/write definition.
6.13.2
Register overview
The SPI interface gives access to all SBC registers; see
Table 4
. The first two bits (A1 and
A0) of the message header define the register address, the third bit is the read register
select bit (RRS) to select one out of two possible feedback registers; the fourth bit (RO)
allows ‘read only’ access to one of the feedback registers. Which of the SBC registers can
be accessed also depends on the SBC operating mode.
Table 4:
Register
address bits
(A1, A0)
Register overview
Operating
mode
Write access (RO = 0)
Read access (RO = 0 or RO = 1)
Read Register Select
(RRS) bit = 0
System Status register
Interrupt Enable Feedback
register
Read Register Select
(RRS) bit = 1
System Diagnosis register
Interrupt register
00
01
all modes
Normal mode;
Standby mode;
Flash mode
Start-up mode;
Restart mode
Normal mode;
Standby mode
Start-up mode;
Restart mode;
Flash mode
Normal mode;
Standby mode
Start-up mode;
Restart mode;
Flash mode
Mode register
Interrupt Enable register
Special Mode register
Interrupt Enable Feedback
register
System Configuration
Feedback register
System Configuration
Feedback register
Special Mode Feedback
register
General Purpose Feedback
register 0
General Purpose Feedback
register 0
10
System Configuration
register
General Purpose register 0
11
Physical Layer Control
register
General Purpose register 1
Physical Layer Control
Feedback register
Physical Layer Control
Feedback register
General Purpose Feedback
register 1
General Purpose Feedback
register 1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UJA1065TW | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:High-speed CAN/LIN fail-safe system basis chip |
| UJA1065TW/3V0 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC HI SPEED CAN SYSTEM RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| UJA1065TW/3V0,512 | 功能描述:CAN 接口集成電路 HI SPEED CAN SYSTEM RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube |
| UJA1065TW/3V0,518 | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC HI SPEED CAN SYSTEM RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| UJA1065TW/3V0512 | 制造商:NXP Semiconductors 功能描述:CONTROLLER SYS CAN/LIN 3V 32HTSSOP |
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