參數(shù)資料
型號: UJA1065
廠商: NXP Semiconductors N.V.
英文描述: High-speed CAN/LIN fail-safe system basis chip
中文描述: 高速的CAN / LIN故障防護(hù)系統(tǒng)基礎(chǔ)芯片
文件頁數(shù): 21/67頁
文件大小: 285K
代理商: UJA1065
9397 750 14409
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Objective data sheet
Rev. 01 — 10 August 2005
21 of 67
Philips Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
If the CAN transceiver enters On-line Listen mode directly from Off-line mode the global
wake-up message is sufficient to wake-up the SBC. This pattern must be received within
t
timeout
after entering On-line Listen mode. Should t
timeout
elapse before receiving the
global wake-up message, then both messages are required for a CAN wake-up.
6.7.3
Termination control
In Active mode, On-line mode and On-line Listen mode, CANH and CANL are terminated
to 0.5 x V
V2
via R
i
. In Off-line mode CANH and CANL are terminated to GND via R
i
. If V2
is disabled due to an overload condition both pins become floating.
6.7.4
Bus, RXD and TXD failure detection
The UJA1065 can distinguish between bus, RXD and TXD failures as indicated in
Table 3
.
All failures are signalled separately in the CANFD bits in the System Diagnosis register.
Any change (detection and recovery) forces an interrupt to the microcontroller, if this
interrupt is enabled.
6.7.4.1
TXDC dominant clamping
If the TXDC pin is clamped dominant for longer than t
TXDC(dom)
the CAN transmitter is
disabled. After the TXDC pin becomes recessive the transmitter is re-activated
automatically when detecting bus activity or manually by setting and clearing the CTC bit.
Fig 9.
CAN wake-up timing diagram.
001aad446
CANH
CANL
wake-up
t
CAN(dom1)
t
CAN(reces)
t
CAN(dom2)
Table 3:
Failure
HxHIGH
HxGND
LxHIGH
LxGND
HxL
Bus dom
TXDC dom
RXDC reces
RXDC dom
CAN-bus, RXD and TXD failure detection
Description
CANH short-circuit to V
CC
, V
BAT14
or V
BAT42
CANH short-circuit to GND
CANL short-circuit to V
CC
, V
BAT14
or V
BAT42
CANL short-circuit to GND
CANH short-circuit to CANL
bus is continuously clamped dominant
pin TXDC is continuously clamped dominant
pin RXDC is continuously clamped recessive
pin RXDC is continuously clamped dominant
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