參數(shù)資料
型號: UJA1065
廠商: NXP Semiconductors N.V.
英文描述: High-speed CAN/LIN fail-safe system basis chip
中文描述: 高速的CAN / LIN故障防護(hù)系統(tǒng)基礎(chǔ)芯片
文件頁數(shù): 40/67頁
文件大?。?/td> 285K
代理商: UJA1065
9397 750 14409
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Objective data sheet
Rev. 01 — 10 August 2005
40 of 67
Philips Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
6.13.11
General purpose registers and general purpose feedback registers
The UJA1065 offers two 12-bit General Purpose registers (and accompanying General
Purpose Feedback registers) with no predefined bit definition. These registers can be
used by the microcontroller for advanced system diagnosis, or for storing critical system
status information outside the microcontroller. After Power-up General Purpose register 0
will contain a ‘Device Identification Code’ consisting of the SBC type and SBC version.
This code is available until it is overwritten by the microcontroller (as indicated by the DIC
bit).
[1]
The Device Identification Control bit is cleared during power-up of the SBC, indicating that General Purpose register 0 is loaded with the
Device Identification Code. Any write access to General Purpose register 0 will set the DIC bit, regardless of the value written to DIC.
[2]
During power-up the General Purpose register 0 is loaded with a ‘Device Identification Code’ consisting of the SBC type and SBC
version, and the DIC bit is cleared.
6.13.12
Register configurations at reset
At Power-on, Start-up and Restart the setting of the SBC registers is predefined. With
external reset events (edge at pin RSTN) the registers will be set as in Start-up mode,
with the exception of the ILEN bit in the System Configuration register.
Table 14:
Bit
15, 14
13
General purpose register 0 and general purpose feedback register 0 bit description
Symbol
Description
Value
A1, A0
register address
10
RRS
Read Register Select
1
0
RO
Read Only
1
Function
read the General Purpose Feedback register 0
read the General Purpose Feedback register 0
read the System Configuration Feedback register
read the register selected by RRS without writing to the
General Purpose register 0
read the register selected by RRS and write to the General
Purpose register 0
General Purpose register 0 contains user defined bits
General Purpose register 0 contains the Device
Identification Code
user defined
user defined
12
0
11
DIC
Device Identification
Control
[1]
1
0
10 to 0
GP0[10:0]
General Purpose bits
[2]
1
0
Table 15:
Bit
15 and 14
13
General purpose register 1 and general purpose feedback register 1 bit description
Symbol
Description
Value
A1, A0
register address
11
RRS
Read Register Select
1
0
RO
Read Only
1
Function
select General Purpose register 1
read the General Purpose Feedback register 1
read the Physical Layer Control Feedback register
read the register selected by RRS without writing to the
General Purpose register 1
read the register selected by RRS and write to the General
Purpose register
the relevant General Purpose bit has been set
the relevant General Purpose bit has been cleared
12
0
11 to 0
GP1[11:0]
General Purpose bits
1
0
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