參數(shù)資料
型號(hào): UJA1065
廠商: NXP Semiconductors N.V.
英文描述: High-speed CAN/LIN fail-safe system basis chip
中文描述: 高速的CAN / LIN故障防護(hù)系統(tǒng)基礎(chǔ)芯片
文件頁數(shù): 56/67頁
文件大小: 285K
代理商: UJA1065
9397 750 14409
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Objective data sheet
Rev. 01 — 10 August 2005
56 of 67
Philips Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
δ
3
duty cycle 3
V
th(reces)(max)
= 0.778
×
V
BAT42
;
V
th(dom)(max)
= 0.616
×
V
BAT42
;
LSC = 1; t
bit
= 96
μ
s;
V
BAT42
= 7 V to 27 V
V
th(reces)(min)
= 0.389
×
V
BAT42
;
V
th(dom)(min)
= 0.251
×
V
BAT42
;
LSC = 1; t
bit
= 96
μ
s;
V
BAT42
= 7.6 V to 27 V
C
RXDL
= 20 pF
[2]
0.417
-
-
δ
4
duty cycle 4
[3]
-
-
0.590
t
p(rx)
propagation delay of
receiver
symmetry of receiver
propagation delay
minimum dominant
time for wake-up of
the LIN-transceiver
continuously
dominant clamped
LIN-bus detection
time
continuously
dominant clamped
LIN-bus recovery
time
TXDL permanent
dominant disable time
-
-
6
μ
s
t
p(rx)(sym)
rising edge with respect to
falling edge; C
RXDL
= 20 pF
Off-line mode
2
-
+2
μ
s
t
BUS(LIN)
30
-
150
μ
s
t
LIN(dom)(det)
Active mode; LIN = 0 V
40
-
160
ms
t
LIN(dom)(rec)
Active mode
0.8
-
2.2
ms
t
TXDL(dom)(dis)
Active mode; TXDL = 0 V
20
-
80
ms
Battery monitoring
t
BAT42(L)
BAT42 LOW time for
setting PWONS
BAT42 LOW time for
setting BATFI
5
-
20
μ
s
t
SENSE(L)
5
-
20
μ
s
Power supply V1; pin V1
t
V1(CLT)
V1 clamped LOW
time during ramp-up
of V1
Start-up mode; V1 active
229
-
283
ms
Power supply V2; pin V2
t
2(CLT)
V2 clamped LOW
time during ramp-up
of V2
V2 active
28
-
36
ms
Power supply V3; pin V3
t
W(CS)
cyclic sense period
V3C = 10; see
Figure 14
V3C = 11; see
Figure 14
V3C = 10; see
Figure 14
V3C = 11; see
Figure 14
14
28
345
345
-
-
-
-
18
36
423
423
ms
ms
μ
s
μ
s
t
on(CS)
cyclic sense on-time
Table 27:
T
vj
=
40
°
C to + 150
°
C; V
BAT42
= 5.5 V to 52 V; V
BAT14
= 5.5 V to 27 V; unless otherwise specified. All voltages are defined
with respect to ground. Positive currents flow into the IC. All parameters are guaranteed over the virtual junction temperature
range by design. Products are 100 % tested at 125
°
C ambient temperature on wafer level (pre-testing). Cased products are
100 % tested at 25
°
C ambient temperature (final testing). Both pre-testing and final testing use correlated test conditions to
cover the specified temperature and power supply voltage range.
Symbol
Parameter
Conditions
Characteristics
…continued
Min
Typ
Max
Unit
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