參數(shù)資料
型號: UJA1065
廠商: NXP Semiconductors N.V.
英文描述: High-speed CAN/LIN fail-safe system basis chip
中文描述: 高速的CAN / LIN故障防護(hù)系統(tǒng)基礎(chǔ)芯片
文件頁數(shù): 31/67頁
文件大小: 285K
代理商: UJA1065
9397 750 14409
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Objective data sheet
Rev. 01 — 10 August 2005
31 of 67
Philips Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
[1]
The nominal watchdog periods are directly related to the SBC internal oscillator. The given values are valid for f
osc
= 512 kHz.
See
Section 6.4.4
.
[2]
[3]
The watchdog is immediately disabled on entering Sleep mode, with watchdog OFF behavior selected, because pin RSTN is
immediately pulled LOW by the mode change. V1 is switched off after pulling pin RSTN LOW to guarantee a safe Sleep mode entry
without dips on V1. See
Section 6.4.4
.
6.13.4
System status register
This register allows status information to be read back from the SBC. This register can be
read in all modes.
11 to 6
NWP[5:0]
Nominal
Watchdog Period
WDPRE = 11(as
set in the Special
Mode register)
001001
001100
010010
010100
011011
100100
101101
110011
110101
110110
14
28
56
112
140
168
196
244
252
280
70
140
280
560
1120
2240
3584
7168
14336
OFF
[2]
70
140
280
560
1120
2240
3584
7168
14336
28672
560
1120
2240
3584
7168
10752
14336
21504
28672
OFF
[3]
Table 6:
Bit
Mode register bit description (bits 11 to 6)
…continued
[1]
Symbol
Description
Value
Time
Normal
mode (ms)
Standby
mode (ms)
Flash mode
(ms)
Sleep mode
(ms)
Table 7:
Bit
15 and 14
13
12
System status register bit description
Symbol
Description
A1, A0
register address
RRS
Read Register Select
RO
Read Only
Value
00
0
1
Function
read System Status register
read System Status register without writing to Mode
register
read System Status register and write to Mode register
0
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