參數(shù)資料
型號: UJA1065
廠商: NXP Semiconductors N.V.
英文描述: High-speed CAN/LIN fail-safe system basis chip
中文描述: 高速的CAN / LIN故障防護系統(tǒng)基礎(chǔ)芯片
文件頁數(shù): 34/67頁
文件大?。?/td> 285K
代理商: UJA1065
9397 750 14409
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Objective data sheet
Rev. 01 — 10 August 2005
34 of 67
Philips Semiconductors
UJA1065
High-speed CAN/LIN fail-safe system basis chip
[1]
V2D will be set when V2 is reactivated after a failure. See
Section 6.6.3.2
.
6.13.6
Interrupt enable register and interrupt enable feedback register
These registers allow setting, clearing and reading back the interrupt enable bits of the
SBC.
1 and 0
CANMD
[1:0]
CAN Mode Diagnosis
11
10
01
00
CAN is in Active mode
CAN is in On-line mode
CAN is in On-line Listen mode
CAN is in Off-line mode, or V2 is not active
Table 8:
Bit
System diagnosis register bit description
…continued
Symbol
Description
Value
Function
Table 9:
Bit
15 and 14
13
Interrupt enable and interrupt enable feedback register bit description
Symbol
Description
A1, A0
register address
RRS
Read Register Select
Value
01
1
0
1
Function
select the Interrupt Enable register
read the Interrupt register
read the Interrupt Enable Feedback register
read the register selected by RRS without writing to
Interrupt Enable register
read the register selected by RRS and write to Interrupt
Enable register
a watchdog overflow during Standby causes an interrupt
instead of a reset event (interrupt based cyclic wake-up
feature)
no interrupt forced on watchdog overflow; a reset is forced
instead
exceeding or dropping below the temperature warning limit
causes an interrupt
no interrupt forced
exceeding or dropping below the GND shift limit causes an
interrupt
no interrupt forced
wrong number of CLK cycles (more than, or less than 16)
forces an interrupt; from Start-up mode and Restart mode a
reset is performed instead of an interrupt
no interrupt forced; SPI access is ignored if the number of
cycles does not equal 16
falling edge at SENSE forces an interrupt
no interrupt forced
clearing of V1D, V2D or V3D forces an interrupt
no interrupt forced
any change of the CAN Failure status bits forces an
interrupt
no interrupt forced
any change of the LIN Failure status bits forces an interrupt
no interrupt forced
12
RO
Read Only
0
11
WTIE
Watchdog Time-out
Interrupt Enable
[1]
1
0
10
OTIE
Over-Temperature
Interrupt Enable
1
0
1
9
GSIE
Ground Shift Interrupt
Enable
0
1
8
SPIFIE
SPI clock count Failure
Interrupt Enable
0
7
BATFIE
BAT Failure Interrupt
Enable
1
0
1
0
1
6
VFIE
Voltage Failure Interrupt
Enable
5
CANFIE
CAN Failure Interrupt
Enable
0
1
0
4
LINFIE
LIN Failure Interrupt
Enable
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UJA1065TW/3V0,512 功能描述:CAN 接口集成電路 HI SPEED CAN SYSTEM RoHS:否 制造商:Texas Instruments 類型:Transceivers 工作電源電壓:5 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:SOIC-8 封裝:Tube
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