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| 型號(hào)： | TSB42AB4I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| 中文描述： | 1394消費(fèi)電子產(chǎn)品鏈路層控制器 |
| 文件頁(yè)數(shù)： | 64/183頁(yè) |
| 文件大?。?/td> | 798K |
| 代理商： | TSB42AB4I |
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412
4.5.2
Packet Insertion Configuration Registers
NOTE:
A
indicates HSDIA port.
B
indicates HSDIB port.
Table 45. Configuration Registers for Packet Insertion
CONFIGURATION REGISTERS
REGISTER NAME
BITS
FUNCTION
INSBUFA_ACC
INSBUFB_ACC
31:0
Access to insertion buffer. The microcontroller can only write the insertion packet to the
insertion buffer when the packet insertion feature is disabled.
INSBUFA_CSR0
INSBUFB_CSR0
30
WRPTR_RST resets the packet insertion buffer write pointer to 0. Only valid when
packet insertion feature is disabled.
29:24
WRPTR indicates the pointer value of the next write access to INSBUFA_ACC. Only
valid when packet insertion feature is disabled
22
RDPTR_RST resets the packet insertion buffer read pointer to 0. Only valid when
packet insertion feature is disabled
21:16
RDPTR indicates the next location that will be returned by a read access to
INSBUFA_ACC. Only valid when packet insertion feature is disabled
10:8
INSRT_BUF indicates to which of the 8 data buffers the packet insertion buffer is
mapped.
7
AUTOFILL all locations in the insertion buffer starting from INSBUFA_WRPTR are
filled with 0xFFFF.
6
PKTINSRT_EN enables the packet insertion feature.
5:0
PKTSIZE indicates size of insertion packet.
INSBUFA_CSR1
INSBUFB_CSR1
15:0
OFPT is used to calculate the time stamp for inserted packets. The format of this
register follows the 16 LSBs of the 1394 cycle timer register.
4.5.3
Packet Insertion Example
A transport stream is transmitted using ceLynx HSDIA port. ceLynx is configured to filter PID values of 0 out
of the transport stream. The application must replace the information contained in PID 0 in the stream
transmitted over 1394.
The application can create a packet to replace the PID 0 packet that was filtered from the transport stream.
The application writes the packet to the ceLynx insertion buffer, and the ceLynx inserts this packet into the
next available gap in the transport stream. These gaps are usually created by the PID filtering function or
by the application not providing data at the interface.
Step 1:
Ensure the packet insertion bit is disabled. This bit is located in
INSBUFx_CSRO.PKTINSRT_EN.
Step 2:
Set up packet insertion size. These bits are located in INBUFx_CSR0.PKTSIZE. For
MPEG2-DVB, these bits are set to 2F, which is the number of quadlets in hex value.
Step 3:
Specify into which stream the empty packets will be inserted. This is accomplished by
programming the buffer of the selected stream in INSBUFx_CSR0.INSRT_BUF.
Step 4:
Set offset packet time value. This time is programmable in INSBUFx_CSR1.
The offset packet time can be thought of as the amount of time allotted for one cell at the HSDI
pins. For example, data is being streamed uniformly into the HSDI:
DATA
A
B
C
D
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| TSB42AB4PGE | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
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相關(guān)代理商/技術(shù)參數(shù) |
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| TSB42AB4IPDT | 功能描述:1394 接口集成電路 1394 Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB42AB4PDT | 功能描述:1394 接口集成電路 1394 Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB42AB4PDTG4 | 功能描述:1394 接口集成電路 Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB42AB4PGE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AC3 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:General purpose link layer ideal for a wide-range of applications |
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