參數(shù)資料
型號(hào): TSB42AB4I
廠商: Texas Instruments, Inc.
英文描述: IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER
中文描述: 1394消費(fèi)電子產(chǎn)品鏈路層控制器
文件頁(yè)數(shù): 121/183頁(yè)
文件大?。?/td> 798K
代理商: TSB42AB4I
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624
0x084 HSDIA_CFG1 – HSDIA Configuration 1
BIT
NAME
TYPE
RESET
FUNCTION
31:15
RSVD
R0
0
Reserved – A write to this location has no effect. A read returns 0s.
14
RXMULTISTREAM
RW
0
Receive multiple streams – Setting this bit to 1 causes the HSDI to
present data at the interface from the buffer selected by the 3-bit
HSDIA address bus. When set to 0 the HSDI retrieves data from
the receive buffer indicated by HSDI_BUFFERS.
13
RSVD
R0
0
Reserved – A write to this location has no effect. A read returns 0.
12
TXMULTISTREAM
RW
0
Transmit multiple streams – Setting this bit to 1 causes the HSDI
to present data at the interface from the buffer selected by the
3-bit HSDIA address bus. When set to 0, the HSDI places the data
into the buffer indicated by HSDI_BUFFERS
11:0
TXDBCNTREND
RW
0
Transmit data block counter end – The binary encoded value
written to this register determines the size of the data blocks
presented at the HSDI when sync mode A or B is used. Values
written to this register have no effect when syncmode C is used.
This is programmed in terms of hex bytes.
0x088 HSDIA_INT – HSDIA Interrupts
BIT
NAME
TYPE
RESET
FUNCTION
31:9
RSVD
R0
0
Reserved – A write to this location has no effect. A read returns 0s.
8
INSRTCMPLT
RCU
0
Packet insertion complete – This interrupt indicates that a packet
has been inserted into the transport stream by the packet
insertion hardware. The packet insert hardware has been auto-
matically disabled when this bit is set and must be re-enabled by
software before packets can be inserted into the transport stream.
7:1
RSVD
R0
0
Reserved – A write to this location has no effect. A read returns 0s.
0
TXOVERRUN
RCU
0
Transmit overrun – This interrupt indicates that the HSDI input
buffer has been overrun by the application and data has been lost.
0x08C HSDIA_INTEN – HSDIA Interrupt Enables
BIT
NAME
TYPE
RESET
FUNCTION
31:9
RSVD
R0
0
Reserved – A write to this location has no effect. A read returns
0s.
8
INSRTCMPLT
RW
0
Packet insertion complete interrupt enable – When this bit is set
to 1, the SYSINT.HSDIAINT bit is set to 1 when the
corresponding bit in the HSDIA_INT register is set by hardware.
When set to 0, the corresponding bit in the HSDIA_INT register
has no effect on the SYSINT.HSDIAINT bit.
7:1
RSVD
R0
0
Reserved – A write to this location has no effect. A read returns
0s.
0
TXOVERRUN
RW
0
Transmit overrun interrupt enable – When this bit is set to 1, the
SYSINT.HSDIAINT bit is set to 1 when the corresponding bit in
the HSDIA_INT register is set by hardware. When set to 0, the
corresponding bit in the HSDIA_INT register has no effect on the
SYSINT.HSDIAINT bit.
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