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參數(shù)資料
| 型號： | TSB42AB4I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| 中文描述： | 1394消費電子產(chǎn)品鏈路層控制器 |
| 文件頁數(shù)： | 112/183頁 |
| 文件大?。?/td> | 798K |
| 代理商： | TSB42AB4I |
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615
0x040 LCTRL – Link Control (Continued)
BIT
NAME
TYPE
RESET
FUNCTION
24
ACCELEN
RW
0
Acceleration enable – When this bit is set, fly-by acceleration and
accelerated arbitration are enabled. This bit cannot be set while
TXEN and RXEN are set. This bit may only be set to 1 when an
IEEE-1394.a capable PHY is used.
23
CONCATEN
RW
0
Concatenation enable – When set to 1, the link may concatenate
multiple isochronous or asynchronous packets. This bit may only
be set to 1 when an IEEE-1394.a capable PHY is used.
22
EN_IDLE_INSRT
RW
1
Enable idle cycle insertion – When this bit is set, the link layer
inserts one idle state(00) on the PHY/link interface CTL lines
between the PHY transmit state(10) and the link transmit state(11)
as indicated in the IEEE-1394.a standard. When this bit is not set,
the interface conforms to the signaling specified in the
IEEE-1394-1995 specification and an idle state is not inserted.
21
RESETTX
RW
0
Reset transmitter – Writing a 1 to this bit resets all state machines in
the link layer that are involved in transmitting a packet. This bit is
self-clearing.
20
RESETRX
RW
0
Reset receiver – Writing a 1 to this bit resets all state machines in
the link layer that are involved in receiving a packet. This bit is
self-clearing.
19
CONTENDEROUT
RW
1
Contender output – The value written to this register is driven on the
PLI_CNTDR terminal when the pin is configured as an output in
SYSCFR.PINCFG register.
18:16
RSVD
R0
0
Reserved – A write to this location has no effect. A read returns 0s.
15
BUSNRST
RW
0
BUS number reset enable – When this enable bit is set, the bus
number field is reset to 0x3FF when a local bus reset is detected.
14
ENLONGHLD
RW
0
Enable long hold – Writing a 1 to this location causes the
IEEE-1394 acknowledge to be delayed to for the maximum
allowable time before being sent.
13:12
RSVD
R0
0
Reserved – A write to this location has no effect. A read returns 0s.
11
CYCMASTER
RWU
0
Cycle master – When this bit is set and the device is attached to
the root PHY, the cycle master function is enabled. When the
cycle_count field of the cycle timer register increments, the
transmitter sends a cycle-start packet. This bit is automatically
cleared by hardware when a cycle-too-long event is detected
according to the IEEE-1394.a specification. The value in this
register cannot be overwritten if CMAUTO is set to 1.
10
CYCTOOLONGDIS
RW
0
Cycle too long disable – When this bit is set, the CYCMASTER bit is
not cleared in response to a cycle too long event as defined in the
IEEE-1394.a specification.
9
CYCTIMEREN
RW
0
Cycle timer enable – The cycle timer is enabled to count when this
bit is set to 1. The cycle timer is disabled when the bit is set to 0.
8
CLSIDER
R0W
0
Clear self-ID error – When CLSIDER is set, the self-ID error code
bits are reset to the no error condition.
7
RSVD
R0
0
Reserved – A write to this location has no effect. A read returns 0.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| TSB42AB4IPDT | 功能描述:1394 接口集成電路 1394 Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB42AB4PDT | 功能描述:1394 接口集成電路 1394 Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB42AB4PDTG4 | 功能描述:1394 接口集成電路 Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB42AB4PGE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AC3 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:General purpose link layer ideal for a wide-range of applications |
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