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參數(shù)資料
| 型號： | TSB42AB4I |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| 中文描述： | 1394消費電子產(chǎn)品鏈路層控制器 |
| 文件頁數(shù)： | 113/183頁 |
| 文件大?。?/td> | 798K |
| 代理商： | TSB42AB4I |
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616
0x040 LCTRL – Link Control (Continued)
BIT
NAME
TYPE
RESET
FUNCTION
6:4
SIDERRCODE
RU
0
Self-ID error code contains the error code of the first self-ID error.
The errors are encoded as follows:
000
No error
001
Last self-ID received was not all child ports
010
Received PHY ID in self-ID was not as expected
011
Quadlet not inverted (phase error)
100
PHY ID sequence error (two or more gaps in IDs)
101
PHY ID sequence error (large gap in IDs)
110
PHY ID error within packet
111
Quadlet not the inversion of the prior quadlet
3
CMAUTO
RW
0
Cycle master automatic set – When CMAUTO is set high, the device
automatically enables CYCMASTER when this node becomes the root
following a bus reset.
2:0
RSVD
R0
0
Reserved – A write to this location has no effect. A read returns 0s.
0x044 LINT – Link Interrupts
BIT
31:22
21
NAME
TYPE
R0
RCU
RESET
0
0
FUNCTION
RSVD
HDRERR
Reserved – A write to this location has no effect. A read returns 0s.
Header error – This bit is set when the receiver detects a CRC error in
the header of a packet that may have been addressed to this node. An
interrupt is generated when the corresponding enable bit in LINTEN is
set. Write 1 to clear.
Self-ID error – This bit is set to 1 to indicate that a self ID packet with
errors has been received. An interrupt is generated when the
corresponding enable bit in LINTEN is set. Write 1 to clear.
20
SIDERR
RCU
0
19
ISOARBFAIL
RCU
0
Isochronous arbitration failed – When set to 1, the isochronous transmit
request to send an isochronous packet failed to win bus arbitration. An
interrupt is generated when the corresponding enable bit in LINTEN is
set. Write 1 to clear.
Cycle too long – This bit is set by hardware when a cycle has exceeded
the maximum allowable time. The hardware simultaneously clears the
LCTRL.CYCMASTER bit when setting this bit. An interrupt is generated
when the corresponding enable bit in LINTEN is set. Write 1 to clear.
Cycle lost – When set to 1, the cycle timer has rolled over twice without
the reception of a cycle start packet. This occurs only when this node is
not cycle master. An interrupt is generated when the corresponding
enable bit in LINTEN is set. Write 1 to clear.
Cycle arbitration failed – When this bit is set to 1, cycle arbitration has
failed. An interrupt is generated when the corresponding enable bit in
LINTEN is set. Write 1 to clear.
18
CYCTOOLONG
RCU
0
17
CYCLOST
RCU
0
16
CYCARBFAIL
RCU
0
15:11
10
RSVD
PHYINT
R0
RCU
0
0
Reserved – A write to this location has no effect. A read returns 0s.
PHY interrupt – When this bit is set to 1, the PHY has signaled an
interrupt through the PHY interface. An interrupt is generated when the
corresponding enable bit in LINTEN is set. Write 1 to clear.
9
PHYREGRX
RCU
0
PHY register received – When set to 1, a register value has been
transferred to the PHY access register from the PHY interface. An
interrupt is generated when the corresponding enable bit in LINTEN is
set. Write 1 to clear.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| TSB42AB4IPDT | 功能描述:1394 接口集成電路 1394 Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB42AB4PDT | 功能描述:1394 接口集成電路 1394 Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB42AB4PDTG4 | 功能描述:1394 接口集成電路 Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB42AB4PGE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AC3 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:General purpose link layer ideal for a wide-range of applications |
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