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參數(shù)資料
| 型號(hào)： | TSB42AA9IPZT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS |
| 中文描述： | STORAGELYNX 1394鏈路層的ATA控制器/ ATAPI儲(chǔ)存產(chǎn)品 |
| 文件頁(yè)數(shù)： | 89/183頁(yè) |
| 文件大?。?/td> | 798K |
| 代理商： | TSB42AA9IPZT |
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524
When a buffer is in this mode, the H0 headers of all DV streams currently on the bus are received by the
DV buffer. An H0 packet is defined as a DV packet with the DIF block number equal to 0. When this DIF block
is received the following 6 quadlets of data are input into the buffer (packet control token, 1394 header, CIP0,
CIP1, and first 8 bytes of H0). The packet control token is the first quadlet input into the buffer. The remaining
quadlets are input into the buffer in the order they were received.
ceLynx continues to receive the DV headers in the buffer until the buffer overflows. Once the buffer
overflows, no more data will be received by the buffer. If the application needs the latest header information,
the software performs a buffer flush and reads the headers from the buffer using the host port.
5.5.3.7
Initial Packet Transmit Delay
The transmit buffer has a programmable amount of data before sending out the first DV packet. This feature
is controlled by the VxDV_THMODE and VxDV_THSEL bits in the transmit data path CFRs. X indicates
HSDIA or HSDIB. VxDV_THMODE turns on the feature. VxDV_THSEL allows the application to choose the
data offset value.
5.5.3.8
Receiving DV Headers for Enabled DV Channel
ceLynx supports a buffer configuration that allows the user to receive DV data in one buffer while receiving
the headers and packet token for that same data in another buffer. ceLynx saves the packet token, 1394
header, CIP headers, and the first two quadlets of the H0 header for the single stream that is being received.
Two buffers should be set up for DV receive. The data packet is received in the higher numbered buffer. The
headers and packet control token are saved in the lower numbered buffer.
The headers and packet control token are saved to the buffer until it is full. No more data is saved once it
is full. The software should flush the buffer to receive the latest header information.
In the header RX buffer, set the RXDP(N)CFG0.INSERTPKTTOKEN bit to 0 for correct operation. The
packet control token is still included at the end of received headers. The packet control token takes the same
form as isochronous receive.
5.5.3.9
Triggering the HSDI_AV Signal
When receiving DV data the available signal goes active when either the receive buffer has 1 quadlet
pending in the buffer.
5.5.4
DV Receive
ceLynx can be formatted to strip any of the 1394 isochronous or CIP headers and time stamp from received
packets before data is stored in the data buffer.
Table 521. Receive Header Stripping
DV RECEIVE PACKET
HEADERS
REGISTER BITS USED TO STRIP
HEADERS
ISO HEADER
RXDP(N)CFG0.STRIPHDR0
CIP0
RXDP(N)CFG0.STRIPHDR1
CIP1/TIME STAMP
RXDP(N)CFG0.STRIPHDR2
DVH0_0
Cannot be stripped on receive
DVH0_1
Cannot be stripped on receive
NOTE:
The RXDPB(N)CFG3 and RXDPB(N)CFG4 registers allow ceLynx to filter
incoming packets. ceLynx can receive packets based on source ID, data length,
or header 0 information. The MASK bits allow the filter to mask off bits of the
incoming packet.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB42AB4I | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AB4PGE | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB43AA82A1 | 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器) |
| TSB81BA3I | IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER |
| TSE-0155-32S-P1-3 | SINGLE MODE SINGLE FIBER TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB42AA9PZT | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB42AA9PZTR | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| TSB42AB4 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AB4I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AB4IPDT | 功能描述:1394 接口集成電路 1394 Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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