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參數(shù)資料
| 型號： | TSB42AA9IPZT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS |
| 中文描述： | STORAGELYNX 1394鏈路層的ATA控制器/ ATAPI儲存產(chǎn)品 |
| 文件頁數(shù)： | 53/183頁 |
| 文件大?。?/td> | 798K |
| 代理商： | TSB42AA9IPZT |
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41
4 Internal Functions
4.1
Data Buffers
4.1.1
Byte Stacking and Endianness
All access to and from the internal transmit and receive FIFOs is 32 bits wide. Since the HSDI is only 8 bits
(or one byte) wide, a byte stack/unstack operation must be performed at the HSDI data port. The order in
which bytes are stacked/unstacked determines the endianness. This
endianness
is programmable. (note
that the endianess setting does not affect the stacking of individual bits into the first byte buffer for the serial
mode. This stacking is fixed and always expects to receive the bits in order
Selecting big endian would put the first byte received into the most significant bit location of the stacking
buffer, and each consecutive byte into successively lower significant byte locations. Selecting little endian
would put the first byte received into the least significant byte location and each consecutive byte into
successively higher significant byte locations.
The endianess of the byte stacking operation can be programmed to either
little endian
or
big endian
(default) independently for each port.
4.1.2
Buffer Overflow/Underflow Status
The
GPIO
signals can be used for applications where the HSDI host needs to burst data into a ceLynx
transmit buffer and will need a look ahead indicator of the buffer’s content status. This allows for a more
efficient memory transfer from the applications memory space to the transmit FIFO since the host controller
could start and stop memory transfers on appropriate boundaries. The full and empty levels of each buffer
are programmable via CFRs by the host controller to allow the user customization when the controller is
notified of a pending full or empty status. Since these signals are application dependent, they are routed
to multifunction pins (
GPIO
) on the device. The buffers also have programmable watermarks, which can
cause interrupts to the external CPU.
4.1.3
Data Buffer Setup
The data buffer can be programmed in up to eight different partitions. Because of this, the registers are
usually described once, but have eight different instances to control the eight different buffers. For example,
the DB(N)CFG0 register is the description for HSDI buffer settings. The actual settings for buffer 0 are
programmed in register 0x15C. The settings for buffer 1 are programmed in register 0x174.
The data buffers have default settings for data type and direction. The transmit data path has default values
for header registers which match the buffer defaults.
If the buffer defaults are changed, the header registers must be reprogrammed to reflect the change.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB42AB4I | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AB4PGE | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB43AA82A1 | 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器) |
| TSB81BA3I | IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER |
| TSE-0155-32S-P1-3 | SINGLE MODE SINGLE FIBER TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB42AA9PZT | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB42AA9PZTR | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| TSB42AB4 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AB4I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AB4IPDT | 功能描述:1394 接口集成電路 1394 Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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