- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385949 > TSB42AA9IPZT (Texas Instruments, Inc.) STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS PDF資料下載
參數(shù)資料
| 型號： | TSB42AA9IPZT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS |
| 中文描述： | STORAGELYNX 1394鏈路層的ATA控制器/ ATAPI儲存產(chǎn)品 |
| 文件頁數(shù)： | 45/183頁 |
| 文件大?。?/td> | 798K |
| 代理商： | TSB42AA9IPZT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁當前第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁
320
Table 37. HSDI Critical Timing Parameters
DESCRIPTION
Setup time, HSDIx_SYNC to HSDIx_CLK
Setup time, HSDIx_RW to HSDIx_CLK
Setup time, HSDIx_EN to HSDIx_CLK
Setup time, HSDIx_DATA to HSDIx_CLK
Clock frequency, byte wide mode
Clock frequency, serial mode
Hold time, HSDIx_CLK to HSDIx_SYNC
Hold time, HSDIx_CLK to HSDIx_EN
Hold time, HSDIx_CLK to HSDIx_DATA, ADDR
Setup time, address to HSDIx_CLK
HSDIx_CLK to HSDIx_D[7:0], byte wide mode
HSDIx_CLK to HSDIx_D[7:0], serial mode
For HSDI Read operation only
All timing examples are shown with a byte-wide data bus. Serial access would be identical. A full byte must
be written or read before HSDIx_EN can be deactivated.
3.3
PHY-Link Interface
The physical layer interface (PHY) of the ceLynx conforms to the description and definition in Section 5 of
the 1394.a specification. The interface is capable of transmitting and receiving at speeds up to 400 Mbps.
The TI bus holder method of dc isolation is included in the ceLynx device. Only a single capacitor on the
PHY-link interface signals needs to be added to implement isolation.
3.4
Two-Wire Serial Interface
The two-wire serial interface gives the system an easy way to load ceLynx configuration registers on power
up or reset. It also makes manufacturing easy, because the individual global unique ID (GUID) is easier to
implement in EEPROM.
ceLynx automatically reads from the two-wire serial interface port on power up or reset. The host controller
is not involved. The software can also initiate a two-wire serial interface reload by CFR. ceLynx can only
interface to one EEPROM and is always the master. ceLynx samples the SCL pin at power up to determine
if an EEPROM is present. The two-wire serial interface port can be disabled by tying the SCL signal to
ground.
The ceLynx two-wire serial interface consists of two active signals, serial data line (SDA) and serial clock
line (SCL), and an internal ground connection. These two signals interface to any 3.3-V EEPROM designed
for two-wire serial interfaces. Since ceLynx is master, the SCL is used as an output. This clock frequency
is generated by ceLynx and is a maximum of 100 kHz.
When ceLynx performs a read of the two-wire serial interface, the data is written directly to the intended
hardware configuration register. No assistance from the application is necessary. The data and address can
be monitored in the serial STAT0 and serial STAT1 registers for test purposes only. The information in these
registers is valid for one two-wire serial interface clock, or 120 SCLKs.
The 1394 command and status registers that are not implemented in ceLynx hardware, such as the
configuration ROM, can be configured to load from EEPROM to an internal buffer. When the two-wire serial
interface read operation is finished, as signaled by an interrupt, the host controller can load these values
from the data buffer to the correct address space.
3.4.1
Two-Wire Serial-Interface Bus Protocol
A start-condition generated from ceLynx starts an action at the two-wire serial interface-bus. While every
communication is 8 bits, a ninth
bit acknowledge is needed. The first bit is the MSB, the eighth is the LSB.
PARAMETER
t0
t1
t2
t3
MIN
MAX
UNIT
ns
ns
ns
ns
4
12
4.6
4
t4
10 K
10 K
27 M
66 M
Hz
t5
t6
t7
t8
0
0
0
ns
ns
ns
ns
14
12
8
ns
t9
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TSB42AB4I | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AB4PGE | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB43AA82A1 | 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器) |
| TSB81BA3I | IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER |
| TSE-0155-32S-P1-3 | SINGLE MODE SINGLE FIBER TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB42AA9PZT | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB42AA9PZTR | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| TSB42AB4 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AB4I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AB4IPDT | 功能描述:1394 接口集成電路 1394 Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。