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參數(shù)資料
| 型號(hào)： | TSB42AA9IPZT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS |
| 中文描述： | STORAGELYNX 1394鏈路層的ATA控制器/ ATAPI儲(chǔ)存產(chǎn)品 |
| 文件頁(yè)數(shù)： | 44/183頁(yè) |
| 文件大小： | 798K |
| 代理商： | TSB42AA9IPZT |
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319
3.2.6
The following explains timing for HSDI multistream modes. These are modes where the HSDI accesses
different buffers by changing the HSDIx_ADDR lines.
HSDI Functional Timing for Multistream Modes
HSDIx_CLK
HSDIx_SYNC
HSDIx_RW
HSDIx_AV
HSDIx_EN
HSDIx_ADDR
HSDIx_DATA
XX
XX
01
02
03
04
01
02
03
04
XX
Figure 324. Functional Timing for Multistream Mode (Read and Write)
The first access is a read. The application should address the read buffer by default and monitor
the HSDIx_AV signal. The HSDIx_AV signal is not asserted unless that specific read buffer is
addressed. The application can also watch the RCVPKT interrupt for the specified read buffer
to determine when to drive the HSDIx_ADDR line.
a.
The application drives the HSDIx_RW signal to indicate a read. It also drives the
HSDIx_ADDR signals to address the read buffer. In general, these two signals must be
driven for at least two HSDIx_CLK cycles before the HSDIx_EN can be driven.
b.
HSDIx_AV goes active at the same time as HSDIx_SYNC and HSDIx_DATA.
c.
The application asserts HSDIx_EN two clock cycles after the address and RW lines have
been asserted. Data is read out of the interface. In this case, the application had asserted
HSDIx_EN and HSDIx_RW one HSDIx_CLK before the HSDI_AV before driving the
HSDIx_EN signal.
d.
The application drives HSDIx_EN low when HSDIx_AV is low. The read is complete.
The second access is a write.
a.
The HSDIx_RW signal is driven low to indicate a write. The HSDIx_ADDR is asserted for
the specified buffer. These signals must be valid for two HSDIx_CLK cycles before enable
or data.
b.
HSDIx_EN is driven high at the same time as HSDIx_SYNC and HSDIx_DATA.
c.
Data is written to the desired buffer. Write is complete when HSDIx_EN is disabled.
HSDI Critical Timing
1.
2.
3.2.7
HSDIx_CLK
HSDIx_SYNC
HSDIx_RW
HSDIx_AV
HSDIx_EN
HSDIx_A[2:0]
HSDIx_D[7:0]
000h
XX
Byte 1
Byte 2
Byte 3
Byte 4
XX
XX
First
t7
t6
t0
t1
t2
t3
XX
t8
t4
XX
t9
Figure 325. HSDI Interface Critical Timing
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB42AA9PZT | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB42AA9PZTR | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| TSB42AB4 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AB4I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AB4IPDT | 功能描述:1394 接口集成電路 1394 Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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