參數(shù)資料
型號(hào): TSB42AA9IPZT
廠商: Texas Instruments, Inc.
英文描述: STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS
中文描述: STORAGELYNX 1394鏈路層的ATA控制器/ ATAPI儲(chǔ)存產(chǎn)品
文件頁(yè)數(shù): 100/183頁(yè)
文件大小: 798K
代理商: TSB42AA9IPZT
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63
6.2.2
SYS CFR Bit Descriptions
0x000 ID – Chip Identification Number
BIT
NAME
TYPE
RESET
FUNCTION
31:0
ID
R
731992x0
Identification – The value in this register is hardwired to
0x7319 92x0. Future revisions may be indicated by a change in
the lower byte.
This document covers the following parts/IDs:
TSB42AA4 0x7319 92C0
TSB42AB4 0x7319 92B0
0x004 PINCFG – Pin Configuration
BIT
NAME
TYPE
RESET
FUNCTION
31:28
GPIOINT1SEL
RW
F
GPIO interrupt 1 select – The binary encoded value in this register
selects one of the 10 GPIOs as the interrupt source for
SYSINT.GPIOINT1. No interrupt source is selected when any value
greater than 1001b is written to this field.
27:24
GPIOINT0SEL
RW
F
GPIO interrupt 0 select – The binary encoded value in this register
selects one of the 10 GPIOs as the interrupt source for
SYSINT.GPIOINT0. No interrupt source is selected when any value
greater than 1001b is written to this field.
23
HSDIAAVPOL
RW
1
HSDIA AV polarity – The value written to this location indicates the
active level of the associated pin. 1active high, 0active low
22
HSDIARWPOL
RW
1
HSDIA RW polarity The value written to this location indicates the
active level of the associated pin. 1active high, 0active low
21
HSDIAENPOL
RW
1
HSDIA EN polarity The value written to this location indicates the
active level of the associated pin. 1active high, 0active low
20
HSDIASYNCPOL
RW
1
HSDIA SYNC polarity The value written to this location indicates
the active level of the associated pin. 1active high, 0active low
19
HSDIBAVPOL
RW
1
HSDIB AV polarity – The value written to this location indicates the
active level of the associated pin. 1active high, 0active low
18
HSDIBRWPOL
RW
1
HSDIB RW polarity The value written to this location indicates the
active level of the associated pin. 1active high, 0active low
17
HSDIBENPOL
RW
1
HSDIB EN polarity The value written to this location indicates the
active level of the associated pin. 1active high, 0active low
16
HSDIBSYNCPOL
RW
1
HSDIB SYNC polarity The value written to this location indicates
the active level of the associated pin. 1active high, 0active low
15
ISOLATION_DIS
RW
0
Bus holder isolation disable bit – When set to 1, the bus holder
isolation for the PHY-link interface is disabled.
14:13
RSVD
R0
0
Reserved – A write to this location has no effect. A read returns 0s.
12
CONTENDEROE
RW
0
Contender output enable – Determines the direction of the
PLI_CNTDR pin on the PHY/link interface. When set to 1, the device
drives the PLI_CNTDR pin as an output. When set to 0, the
PLI_CNTDR pin is an input to the device.
11:10
RSVD
R0
0
Reserved – A write to this location has no effect. A read returns 0s.
9
MCINTZFLT
RW
1
Programmable microcontroller interrupt interrupt float When this
bit is set to 1, the microcontroller interface INTZ pin output driver is
turned off unless the signal is actively asserted.
8
MCACKZFLT
RW
1
Programmable microcontroller acknowledge float When this bit is
set to 1, the microcontroller interface MCIF_ACKZ pin output driver
is turned off when the signal is not actively asserted.
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