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參數(shù)資料
| 型號： | TSB42AA9IPZT |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS |
| 中文描述： | STORAGELYNX 1394鏈路層的ATA控制器/ ATAPI儲存產(chǎn)品 |
| 文件頁數(shù)： | 63/183頁 |
| 文件大?。?/td> | 798K |
| 代理商： | TSB42AA9IPZT |
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4.5
Isochronous Packet Insertion, Transmit Only
This feature has been included in ceLynx specifically to support modification of the PAT and PMT packets
of the MPEG2 standard ISO/IEC 13818-1.
4.5.1
Functional Overview
ceLynx supports packet insertion into a sparse MPEG2 transport stream. A sparse MPEG2 stream is
defined as a stream that contains gaps between some packets, and the gaps are larger than a single packet.
There are two memory areas dedicated to packet insertion. The insertion buffers are a maximum of 188
bytes in length. These buffers are accessible via the microcontroller interface. Each buffer is dedicated to
one HSDI.
ceLynx supports transmission of two independent MPEG2 transport streams. To minimize the complexity
of the insertion buffer logic, the HSDI must be configured in fixed buffer mode. As a result of these
requirements, no more than one transport stream, either DVB or DirecTV, can be input into each HSDI when
the packet insertion logic is enabled. Supporting packet insertion for two independent MPEG2 transport
steams requires that each HSDI be dedicated to one transport stream.
Both insertion buffers are write accessible via the microprocessor interface. Each insertion buffer has an
address counter. Upon
system reset or power up
the address counter of each buffer is set to 0x0. The
insertion buffers are written as follows:
1.
2.
3.
The microcontroller writes a word to the insertion buffer address.
The data is written directly to the insertion buffer at the address pointed to by the address counter.
The address counter is incremented.
Once
n
words are written to an insertion buffer, the packet is enabled for transport by setting the insertion
buffer enable bit. The setting of the enable bit is performed by software. The packet is inserted into the
stream at the next available packet gap. Once an insertion buffer has its ENABLE bit set, all writes to that
buffer are ignored.
If the number of
n
words is less than the insertion buffer size for a DVB stream, then the AUTOFILL function
can be used. When AUTOFILL is set, the remainder of the packetsize-n words are written to 0xFFFFFFFF.
The packet size for each insertion buffer is determined by DB(N)CFG0.STREAMTYPE.
Once a packet has been enabled for insertion into a transport stream, the hardware inserts the packet in
the next available gap. Packets are inserted in the HSDI as if the data were coming in through the HSDI.
When the HSDI is inactive (i.e., no data is being clocked in and the last packet has been completed) the
insertion packet begins to be input into the system. The insertion packet is time-stamped just as a packet
would be coming in through the HSDI. An insertion packet does not pass through the PID filter.
If a packet begins to enter the HSDI before the insertion packet has been completely input, the part of the
insertion packet that has been written to the TX buffer is flushed and the pointers are reset. The incoming
packet is accepted. The incoming packet is not delayed in any way. An aborted insertion attempt does not
cause an interrupt. During the next available gap another attempt is made to insert the packet. This
continues until the insertion buffer is disabled by software or the packet is successfully inserted into the
buffer.
If the buffer overflows when the insertion packet is inserted, the part of the insertion packet that has been
written to the TX buffer is flushed and the pointers are reset. An aborted insertion attempt does not cause
an interrupt.
Once a packet has been inserted into the transport stream the microcontroller is interrupted. The packet
insertion logic is then disabled. The software must re-enable the insertion buffer to insert another packet.
相關(guān)PDF資料 |
PDF描述 |
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| TSB42AB4I | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AB4PGE | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB43AA82A1 | 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB42AA9PZT | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TSB42AA9PZTR | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| TSB42AB4 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AB4I | 制造商:TI 制造商全稱:Texas Instruments 功能描述:IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| TSB42AB4IPDT | 功能描述:1394 接口集成電路 1394 Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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