參數(shù)資料
型號(hào)： TSB42AA9IPZT
廠(chǎng)商： Texas Instruments, Inc.
英文描述： STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS
中文描述： STORAGELYNX 1394鏈路層的ATA控制器/ ATAPI儲(chǔ)存產(chǎn)品
文件頁(yè)數(shù)： 115/183頁(yè)
文件大小： 798K
代理商： TSB42AA9IPZT
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618
0x048 LINTEN – Link Interrupt Enables (Continued)
BIT
10
NAME
TYPE
RW
RESET
0
FUNCTION
PHYINT
PHY interrupt enable – When this bit is set to 1, the SYSINT.LLCINT0 bit
is set to 1 when the corresponding bit in the LINT register is set by
hardware. When set to 0, the corresponding bit in the LINT register has
no effect on the SYSINT.LLCINT0 bit.
PHY register received interrupt enable –When this bit is set to 1, the
SYSINT.LLCINT0 bit is set to 1 when the corresponding bit in the LINT
register is set by hardware. When set to 0, the corresponding bit in the
LINT register has no effect on the SYSINT.LLCINT0 bit.
PHY bus reset interrupt enable – When this bit is set to 1, the
SYSINT.LLCINT0 bit is set to 1 when the corresponding bit in the LINT
register is set by hardware. When set to 0, the corresponding bit in the
LINT register has no effect on the SYSINT.LLCINT0 bit.
Reserved – A write to this location has no effect. A read returns 0.
Cycle seconds interrupt enable – When this bit is set to 1, the
SYSINT.LLCINT0 bit is set to 1 when the corresponding bit in the LINT
register is set by hardware. When set to 0, the corresponding bit in the
LINT register has no effect on the SYSINT.LLCINT0 bit.
Cycle start interrupt enable – When this bit is set to 1, the
SYSINT.LLCINT0 bit is set to 1 when the corresponding bit in the LINT
register is set by hardware. When set to 0, the corresponding bit in the
LINT register has no effect on the SYSINT.LLCINT0 bit.
Cycle done interrupt enable – When this bit is set to 1, the
SYSINT.LLCINT0 bit is set to 1 when the corresponding bit in the LINT
register is set by hardware. When set to 0, the corresponding bit in the
LINT register has no effect on the SYSINT.LLCINT0 bit.
Reserved – A write to this location has no effect. A read returns 0s.
Arbitration reset gap interrupt enable – When this bit is set to 1, the
SYSINT.LLCINT0 bit is set to 1 when the corresponding bit in the LINT
register is set by hardware. When set to 0, the corresponding bit in the
LINT register has no effect on the SYSINT.LLCINT0 bit.
Sub action gap interrupt enable – When this bit is set to 1, the
SYSINT.LLCINT0 bit is set to 1 when the corresponding bit in the LINT
register is set by hardware. When set to 0, the corresponding bit in the
LINT register has no effect on the SYSINT.LLCINT0 bit.
9
PHYREGRX
RW
0
8
PHYBUSRST
RW
0
7
6
RSVD
CYCSEC
R0
RW
0
0
5
CYCSTART
RW
0
4
CYCDONE
RW
0
3:2
1
RSVD
ARBRSTGAP
R0
RW
0
0
0
SUBACTGAP
RW
0
0x04C LCYCTIM – Link Cycle Timer
BIT
NAME
TYPE
RESET
FUNCTION
31:25
CYCSEC
RWU
0
Cycle seconds – 1-Hz cycle timer counter. This counter increments
whenever the LCYCTIM.CYCNUMBER field rolls over from 7999 to 0.
Cycle number – 8-kHz cycle timer. This counter increments whenever
LCYCTIM.CYCOFFSET rolls over from 3071 to 0.
24:12
CYCNUMBER
RWU
0
11:0
CYCOFFSET
RWU
0
Cycle offset – This field counts from 0 to 3071 and rolls over once every
125
μ
s.
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB42AA9PZT 制造商:Rochester Electronics LLC 功能描述:- Bulk
TSB42AA9PZTR 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel
TSB42AB4 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER
TSB42AB4I 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER
TSB42AB4IPDT 功能描述:1394 接口集成電路 1394 Link Layer Cntrlr RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
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