參數(shù)資料
型號: TSB42AA4PGE
廠商: Texas Instruments, Inc.
英文描述: IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER
中文描述: 1394消費(fèi)電子產(chǎn)品鏈路層控制器
文件頁數(shù): 71/183頁
文件大小: 798K
代理商: TSB42AA4PGE
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56
Table 56. Asynchronous Receive Control (Continued)
CONTROL BIT
CSR
ASYNCHRONOUS PACKET RECEIVED
Destination address: bus, node, FFFFF, F000000
If set, then all asynchronous packets addressed to CSR space specified by IEEE 1212.r and
13941995 are received by the selected buffer. This only includes packets with destination address
between (bus, node, FFFFF, 00001FF
bus, node, FFFFF, F0003FF). This does not include PHY
packets, self-ID packets, or broadcast packets.
Destination address: bus, node, FFFFF, F000200
If set, then all asynchronous packets addressed to serial bus space specified by IEEE 1212.r and
13941995 are received by the selected buffer. This only includes packets with destination address
between (bus, node, FFFFF, 0000200
bus, node, FFFFF, F0003FF). This does not include PHY
packets, self-ID packets, or broadcast packets.
Destination address: bus, node, FFFFF, F000400
If set, then all asynchronous packets addressed to configuration ROM space specified by IEEE
13941995 are received by the selected buffer. This only includes packets with destination address
between (bus, node, FFFFF, F000400
bus, node, FFFFF, F0007FF). This does not include PHY
packets, self-ID packets, or broadcast packets.
Destination address: bus, node, FFFFF, F000800
If set, then all asynchronous packets addressed to initial unit space specified by IEEE 13941995
are received by the selected buffer. This only includes packets with destination address between
(bus, node, FFFFF, F000800
bus, node, FFFFF, FFFFFFF). This does not include PHY packets,
self-ID packets, or broadcast packets.
bus, node, FFFFF, F0001FF
SERBUS
bus, node, FFFFF, F0003FF
ROM
bus, node, FFFFF, F0007FF
INITUNIT
bus, node, FFFFF, FFFFFFF
In addition to the asynchronous control bits listed in Table 56, the RXDPB(N)CFG2 and RXDPB(N)CFG3
registers allow the ceLynx to receive packets with selected values of the source ID, header 0 values, or data
length. The application must program the selected value in the RXDPB(N)CFG2 and RXDPB(N)CFG3
registers. For example, to receive only asynchronous packets with source ID 1, the application would
program the SRCIDMSK bits (bits 31:16) to 0xFFFF. A 1 in the SRCIDMSK field indicates that bit is
compared with the SRCIDFLTR value. The SRCIDFLTR bits (bits 15:0) program the compare value. In this
example, the application only wants to receive source ID 1. The setting for bits 15:0 would be 0x0001.
Table 57. Asynchronous Receive Header Strip
ASYNCHRONOUS RECEIVE HEADERS
REGISTERS USED FOR HEADER STRIP
Asynchronous packet control token
RXDPB(N)CFG0.INSERTPKTTOKEN
(Packet control token is included if INSERTPKTTOKEN = 1)
Destination ID/tLabel/retry code/tCode/priority
RXDPB(N)CFG0.STRIPHDR0
Source ID/Destination offset high
RXDPB(N)CFG0.STRIPHDR1
DestinationOffsetLow
RXDPB(N)CFG0.STRIPHDR2
DataLength/ Extended tCode (if block packet)
See Figure 56 for exact header format.
RXDPB(N)CFG0.STRIPHDR3
5.2.1
Quadlet Receive
The quadlet-receive format is shown in Figure 56 and is described in Table 58. The first quadlet contains
the packet-control token that is added by ceLynx. The first 16 bits of the second quadlet contain the
destination node and bus ID, and the remaining 16 bits contain packet information. The first 16 bits of the
third quadlet contain the node and bus ID of the source, and the remaining 16 bits of the third quadlet and
the fourth quadlet contain the 48-bit, quadlet-aligned destination offset address. The last quadlet contains
data that is used by write requests and read responses. For read requests and write responses, the quadlet
data field is omitted.
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