參數(shù)資料
型號(hào): TSB42AA4PGE
廠(chǎng)商: Texas Instruments, Inc.
英文描述: IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER
中文描述: 1394消費(fèi)電子產(chǎn)品鏈路層控制器
文件頁(yè)數(shù): 55/183頁(yè)
文件大小: 798K
代理商: TSB42AA4PGE
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)當(dāng)前第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)
43
4.2
Time Stamping and Aging
Most time stamp and aging functionality is controlled through register DB(N)CFG0. The critical control bits
are listed in Table 41. Time stamping is not supported on the host port.
Table 41. Time Stamp and Aging Control Bits
BIT NAME
DESCRIPTION
DB(N)CFG0.TSRELEASE
For receive operation, this control bit holds a packet in the associated buffer until its
time stamp is equal to current cycle timer value. It then releases the packet to the
application.
For transmit operation, this control bit is used to play back prerecorded MPEG2 data. It
holds the data packet until the time stamp (without offset) is equal to the current cycle
time before transmitting the packet over 1394.
DB(N)CFG0.TSAGE
For receive operation, this control bit flushes all packets with expired time stamps in an
associated buffer.
For transmit operation, this control bit flushes packets waiting to be transmitted whose
time stamps equal the current cycle timer value. This is used to prevent ceLynx from
transmitting old MPEG2 packets over 1394.
DB(N)CFG0.TSINSERT
For transmit operations, this control bit adds a time stamp to the transmitted data
stream. This time stamp value is equal to the current cycle timer value plus a
programmable offset.
For receive operations, this control bit strips time stamps from the data in the receive
buffer. This control bit only operates if all other data headers are also stripped.
DB(N)CFG0.TSSTRIP
The ceLynx does not support time stamping of the formatted ISO packets transmitted or received through
the host interface. Time stamp operations are supported only through the HSDI.
4.2.1
Time Stamp and Aging for MPEG2 Data
The ceLynx uses time stamping to preserve the temporal relationship of MPEG2 (DirecTV
) packets in a
transport stream while being transmitted over 1394.
The transmitting ceLynx (transmitting onto 1394) places a time stamp on each MPEG2 cell it transmits. The
time stamp value is the sum of the current value of the 1394 cycle timer and a user programmable transmit
offset value. This value is programmed in register DB(N)CFG2.
The transmitting ceLynx can age a packet (or flush it from the FIFO) if it is not transmitted in time. This is
to avoid transmitting invalid time stamps over 1394. If the packet is not transmitted before the time stamp
plus transmit offset equals the cycle timer, the packet is aged. If transmit aging is used, a transmit offset must
be used.
See Figure 42 for an explanation of packet aging.
Transmit Offset
Packet + Time Stamp
Written To Transmit
Buffer
Packet Aged From
Transmit Buffer if it Has
Not Been Transmitted
Figure 42. MPEG2 Transmit and Aging
The receiving ceLynx decodes the time stamp upon receive. The MPEG2 packet is released to the
application when the incoming time stamp is equal to the current cycle timer. When the data is released to
the application, the HSDI will indicate data is available then the application is able to read data from the
buffer.
相關(guān)PDF資料
PDF描述
TSB42AA9I STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS
TSB42AA9IPZT STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS
TSB42AB4I IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER
TSB42AB4PGE IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER
TSB43AA82A1 1394 integrated PHY and link layer controller(1394集成PHY和鏈路層控制器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB42AA4PGER 制造商:Rochester Electronics LLC 功能描述:- Bulk
TSB42AA9 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS
TSB42AA9A 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:StorageLynx 1394 Link-Layer Controller for ATA/ATAPI Storage Products
TSB42AA9APZT 功能描述:1394 接口集成電路 Hi Perf 1394a 3.3V Link-Layer Cntrlr RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB42AA9APZTG4 功能描述:1394 接口集成電路 3.3V Link-Layer Cntrlr RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray