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| 型號(hào)： | TSB42AA4PGE |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER |
| 中文描述： | 1394消費(fèi)電子產(chǎn)品鏈路層控制器 |
| 文件頁(yè)數(shù)： | 39/183頁(yè) |
| 文件大小： | 798K |
| 代理商： | TSB42AA4PGE |
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314
Table 36. HSDI Synchronization Modes
SYNCHRONIZATION
MODE
FIXED/VARIABLE
LENGTH
DESCRIPTION
Mode A
Fixed
HSDIx_SYNC pin is ignored on transmit and high-impedance on
receive. Used to receive or transmit data blocks that are a fixed
length. The fixed data block length must be programmed in
HSDIxCFG1.TXDBCNTREND.
Mode B
Fixed
HSDI_SYNC is active during the first byte of the data packet.
Used when receiving or transmitting data packet that are fixed
length. The fixed data packet length must be programmed in
HSDIxCFG1.TXDBCNTREND.
Mode C
Variable
HSDI_SYNC is active during the last byte of the transfer. Used to
transmit or receive variable length packets.
3.2.3.1
Mode A (default mode)
This mode is useful especially when a particular type of data with constant packet length is transmitted or
received over the
HSDI
, e.g., DVB data with a packet length of 188 bytes only. The data length (in terms
of bytes) must be written to the HSDIxCFG1 configuration register. An internal counter keeps track of the
beginning of the data packets. During transmit operation, the externally supplied
HSDIx_SYNC
signal is
ignored. During receive operation HSDIx_SYNC is in the high-impedance state.
In the transmit mode, the counter is started when the buffer is enabled. Once the counter reaches the packet
length the packet is terminated and the next valid byte becomes the start of the next packet. To halt the count
and prevent data from being latched, the user can deassert the HSDIx_EN enable. This disables the counter
and prevents the loading of any data. Once the data is valid again the user can reassert the HSDI enable.
In this mode, the
HSDIx_SYNC
signal value is ignored. In the transmit mode, sync mode A is designed for
continuous back-to-back streaming only. For all noncontinuous video streaming, use sync mode B for
correct synchronization of the data. If the application must use sync mode A, configure and enable the HSDI
before the source starts transmitting the data onto the HSDI.
In receive mode, the first occurrence of the HSDIx_AV signal is used as an indication that data is available
in the buffer. If the HSDIx_EN signal is asserted, the first word of the data is present on the data lines, and
in the same cycle the HSDIx_AV signal goes high. The counter counts until the data block ends. If there is
no additional data available, the HSDIx_AV signal goes low in the same cycle as the end of a packet. If
additional data is still available, data continues to stream out of the HSDI. The HSDIx_EN signal can be
deasserted to hold off the HSDI on any byte boundary. While the HSDIx_EN is low, the data does not change.
3.2.3.2
Mode B
Mode B is a common interface found on MPEG2 transport chips on the market today. The data interface
functions exactly as in Mode A with the addition of a synchronization signal.
In mode B, the HSDIx_SYNC signal determines the start of a new packet. The end of a packet is determined
by the internal counter. This means the application can leave enable high after the last byte of data but before
the next active HSDIx_SYNC signal
without
writing incorrect data into the FIFO.
The signal is active during the same cycle as the first byte of each data block. In transmit mode this signal
is an input to the HSDI. The length of a cell must be fixed and is programmed in a configuration register as
in mode A.
3.2.3.3
Mode C
Mode C is provided for standard asynchronous packets. These packets are usually not a fixed length. In
this mode the HSDIx_SYNC signal is used to indicate the end of a packet. The length of the packet is not
programmed in CFRs. On transmit, data is clocked in when HSDIx_EN is active. An asserted HSDIx_SYNC
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