參數資料
型號: TSB42AA4PGE
廠商: Texas Instruments, Inc.
英文描述: IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER
中文描述: 1394消費電子產品鏈路層控制器
文件頁數: 108/183頁
文件大?。?/td> 798K
代理商: TSB42AA4PGE
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611
0x014 SYSINT – System Interrupts and Interrupt Enables (Continued)
BIT
NAME
TYPE
RESET
FUNCTION
15
GPIOINT1
RU
0
GPIO interrupt 1 – This bit is set by hardware when any change occurs
on the GPIO pin selected by PINCFG.GPIOINT1S. This interrupt is
cleared by writing 1 to the associated GPIOCFG.GPIO[N]STAT bit.
14
GPIOINT0
RU
0
GPIO interrupt 0 This bit is set by hardware when any change occurs
on the GPIO pin selected by PINCFG.GPIOINT0S. This interrupt is
cleared by writing 1 to the associated GPIOCFG.GPIO[N]STAT bit.
13
RSVD
R0
0
Reserved – A write to this location has no effect. A read returns 0.
12
MCIFINTR
RU
0
Microcontroller interface interrupt – This bit is set by hardware to
indicate that an assigned interrupt in the MCIFINT register has been
triggered. This bit is cleared when the interrupt is cleared in the
MCIFINT register.
11
RXDPINT1
RU
0
Receive data path interrupt 1 This bit is set by hardware to indicate
that an assigned interrupt in the upper doublet of the RXDPINT register
has been triggered. This bit is cleared when the interrupt is cleared in
the RXDPINT register.
10
RXDPINT0
RU
0
Receive data path interrupt 0 This bit is set by hardware to indicate
that an assigned interrupt in the lower doublet of the RXDPINT register
has been triggered. This bit is cleared when the interrupt is cleared in
the RXDPINT register.
9
TXDPINT1
RU
0
Transmit data path interrupt 1 This bit is set by hardware to indicate
that an assigned interrupt in the upper doublet of the TXDPINT register
has been triggered. This bit is cleared when the interrupt is cleared in
the TXDPINT register.
8
TXDPINT0
RU
0
Transmit data path interrupt 0 This bit is set by hardware to indicate
that an assigned interrupt in the lower doublet of the TXDPINT register
has been triggered. This bit is cleared when the interrupt is cleared in
the TXDPINT register.
7
DBINT3
RU
0
DB interrupt 3 This bit is set by hardware to indicate that an assigned
interrupt in the upper doublet of the DBEINT register has been
triggered. This bit is cleared when the interrupt is cleared in the
DBEINT register.
6
DBINT2
RU
0
DB interrupt 2 This bit is set by hardware to indicate that an assigned
interrupt in the lower doublet of the DBEINT register has been
triggered. This bit is cleared when the interrupt is cleared in the
DBEINT register.
5
DBINT1
RU
0
DB interrupt 1 This bit is set by hardware to indicate that an assigned
interrupt in the upper doublet of the DBINT register has been triggered.
This bit is cleared when the interrupt is cleared in the DBINT register.
4
DBINT0
RU
0
DB interrupt 0 This bit is set by hardware to indicate that an assigned
interrupt in the lower doublet of the DBINT register has been triggered.
This bit is cleared when the interrupt is cleared in the DBINT register.
3
HSDIBINT
RU
0
HSDIB interrupt This bit is set by hardware to indicate that an
assigned interrupt in the HSDIBINT register has been triggered. This
bit is cleared when the interrupt is cleared in the HSDIBINT register.
2
HSDIAINT
RU
0
HSDIA interrupt This bit is set by hardware to indicate that an
assigned interrupt in the HSDIAINT register has been triggered. This
bit is cleared when the interrupt is cleared in the HSDIAINT register.
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