參數(shù)資料
型號(hào): TSB42AA4PGE
廠商: Texas Instruments, Inc.
英文描述: IEEE 1394 A CONSUMER ELECTRONICS LINK LAYER CONTROLLER
中文描述: 1394消費(fèi)電子產(chǎn)品鏈路層控制器
文件頁(yè)數(shù): 169/183頁(yè)
文件大小: 798K
代理商: TSB42AA4PGE
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672
0x340 RXDPCTL Receive Data Path Control (Continued)
BIT
NAME
TYPE
RESET
FUNCTION
9
DBCCRST_B
R0W
0
Data block continuity counter reset B Writing a 1 to this location
causes data block continuity counter B to be synchronously reset.
This bit is self-clearing.
8
DBCCRST_A
R0W
0
Data block continuity counter reset A Writing a 1 to this location
causes data block continuity counter A to be synchronously reset.
This bit is self-clearing.
7
EMPTPKTBEN
RW
0
Empty packet B receive enable – Setting this bit to 1 enables empty
packets of video stream B to be received.
6
EMPTPKTAEN
RW
0
Empty packet A receive enable – Setting this bit to 1 enables empty
packets of video stream A to be received.
5
FLUSHDCRCERR
RW
1
Abort on data CRC error – When this bit is set by hardware, incoming
packets that contain a data CRC error are automatically aborted and
flushed from the associated buffer.
4:3
RSVD
RW
0
Reserved – A write to this location has no effect. A read returns 0s.
2
RXSIDFULL
RW
0
Receive full self-ID packets – Setting this bit to 1 enables both self-ID
packet quadlets to be written into the buffer.
1
ACKTARDYEN
RW
0
Ack tardy enable – Setting this bit to 1 causes all incoming
asynchronous 1394 packets to be acknowledged with an ACK_tardy
(B) acknowledge unless RXDPCTL.BSYALLPKTS is set to 1.
0
BSYALLPKTS
RW
0
Busy all packets – Setting this bit to 1 causes all incoming
asynchronous 1394 packets to be acknowledged with an
ACK_busy_x (4) acknowledge. This bit overrides the function of
RXDPCTL.ACKTARDYEN.
0x344 RXDPSTAT – Receive Data Path Status
BIT
NAME
TYPE
RESET
FUNCTION
31:16
RSVD
R0
0
Reserved – A write to this location has no effect. A read returns 0s.
15:14
STATEMIB
R
0
State encryption mode indicator stream B Shows the EMI status of the
MPEG stream B.
13:12
STATEMIA
R
0
State encryption mode indicator stream A Shows the EMI status of the
MPEG stream A.
11
STATEVODA
R
0
State even/odd bit stream A This even/odd bit stream is extracted from the
header of DVB and DirecTV source packets. It is updated with each packet.
10
STATEVODB
R
0
State even/odd bit stream B This even/odd bit stream is extracted from the
header of DVB and DirecTV source packets. It is updated with each packet.
9:1
RSVD
R0
0
Reserved – A write to this location has no effect. A read returns 0s.
0
VIDSELERR
RU
0
Video select error – This bit is set by hardware to indicate that two buffers
are configured as video type A or B at the same time. This error indication
clears itself when the conflict is resolved.
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PDF描述
TSB42AA9I STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TSB42AA4PGER 制造商:Rochester Electronics LLC 功能描述:- Bulk
TSB42AA9 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:STORAGELYNX 1394 LINK-LAYER CONTROLLER FOR ATA/ATAPI STORAGE PRODUCTS
TSB42AA9A 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:StorageLynx 1394 Link-Layer Controller for ATA/ATAPI Storage Products
TSB42AA9APZT 功能描述:1394 接口集成電路 Hi Perf 1394a 3.3V Link-Layer Cntrlr RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray
TSB42AA9APZTG4 功能描述:1394 接口集成電路 3.3V Link-Layer Cntrlr RoHS:否 制造商:Texas Instruments 類(lèi)型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray