參數(shù)資料
型號： TNET3001
廠商： Texas Instruments, Inc.
英文描述： SONET STS-1 Overhead Terminator(SONET STS-1附加終端)
中文描述： SONET的STS - 1的開銷終結(jié)者（SONET的STS - 1的附加終端）
文件頁數(shù)： 43/49頁
文件大?。?/td> 1090K
代理商： TNET3001
TNETS3001
SONET STS-1 OVERHEAD TERMINATOR
SDNS007B – OCTOBER 1993 – REVISED JUNE 1995
43
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
interfaces and operating modes
The control bits used for various modes are summarized below in the following table:
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0FA
STS-1
PARA
ALTOW
1F9
RXRTM
1FA
SPE
TCLK
RCLK
line-side interface
In the receive direction, the line-side interface consists of the incoming 51.84-MHz clock (RLCI), the incoming
STS-1 data (RLDI), and the optional frame pulse (RFRI). When used, RFRI allows exit from the OOF state within
125
μ
s. The transmit-line interface consists of the reference 51.84-MHz clock (TLCI), the optional frame
reference (TFRI), the outgoing clock (TLCO), and the outgoing STS-1 data (TLDO). The line-side interface
supports either the STS-1 mode or the STS-N mode as summarized in the following table:
MODE
SELECTION
DESCRIPTION
STS-1
STS-1=1
Both incoming and outgoing line data are scrambled. The chip descrambles RLDI and scrambles TLDO.
The receive B1 byte contains B1 BIP-8 parity. The chip compares the incoming B1 byte to calculated B1 and adds
the parity errors to the receive B1 counter.
The transmit B1 byte is the outgoing B1 BIP-8 parity. The chip calculates the outgoing B1 parity, exclusive-ORs the
result with the outgoing B1 error mask from RAM location 149, and transmits the result on the line.
STS N
STS-N
STS 1 0
STS-1=0
Both incoming and outgoing line data are not scrambled.
The receive B1 byte contains B1 BIP-8 parity-error indications. The chip adds the ones in the incoming B1 byte to
the receive B1 counter.
The transmit B1 byte contains the B1 error mask from RAM location 149.
The clock selection bit (TCLK) allows TLCO to be derived from the following sources:
TCLK
SPE
PARA
SOURCE OF TLCO
0
0
0
TTCI. TFRI cannot be used in this mode.
0
0
1
TPCI. TFRI cannot be used in this mode.
1
0
0
TLCI. TFRI can be used in this mode.
1
0
1
TPCI. TFRI can be used in this mode.
TLCI. TFRI can be used in this mode, (SPE only) and serial only.
0,1
1
0
The SPE-only mode can be used only if the control bit RXRTM = 0
terminal-side interface
The receive-direction terminal-side interface consists of the 51.84-MHz serial clock (RTCO), the serial data
(RTDO), the payload indicator (RSPE), the C1J1 indicator (RSYN), the 6.48-MHz parallel clock (TPCO), and
the parallel data (TPDO7–TPDO0). The transmit terminal-side interface consists of the 51.84-MHz serial clock
(TTCI), the serial data (TTDI), the payload indicator (TSPE), the C1J1 or J1 indicator (TSYN), the 6.48-MHz
parallel clock (TPCI), and the parallel data (TPDI7–TPDI0).
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