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參數(shù)資料
| 型號： | TNET3001 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SONET STS-1 Overhead Terminator(SONET STS-1附加終端) |
| 中文描述： | SONET的STS - 1的開銷終結者（SONET的STS - 1的附加終端） |
| 文件頁數(shù)： | 36/49頁 |
| 文件大小： | 1090K |
| 代理商： | TNET3001 |
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TNETS3001
SONET STS-1 OVERHEAD TERMINATOR
SDNS007B – OCTOBER 1993 – REVISED JUNE 1995
36
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
receive line- and terminal-overhead byte RAM locations
SYMBOL
ADDRESS (hex)
CONTROL
BIT
DESCRIPTION
INCOMING
INSERT
036
A1
016
RRFRM
Framing pattern. The A1 and A2 bytes are automatically regenerated and are
stored in insert locations.
A2
017
037
C1
01C
05C
03C
RRC1
STS-1 signal identifier
.
The incoming C1 byte is debounced and stored in
location 05C.
B1
014
034
049
RRB1
Section BIP-8 parity. The received B1 byte carries B1 BIP-8 parity in the STS-1
mode and B1 BIP-8 parity-error indications in the STS-N mode. The parity
errors are added to the receive B1 counter. The B1 BIP-8 parity for the
outgoing terminal data is recalculated and stored in the insert location.
E1
018
038
RRE1
RE2A
RA2E
Section-orderwire byte. The incoming E1 byte is also available in the
orderwire/APS interface. The E1 byte can be reused for AIS communication
between multiple TNETS3001s.
F1
01D
05D
03D
RRF1
Section-user byte. The F1 byte is debounced and stored in location 05D.
D1
D2
D3
005
006
007
025
026
027
RRSD
Section data-communication channel
.
The incoming D1, D2, and D3 bytes are
available as a single 192-kbit/s serial HDLC channel on the section-datacom
interface.
H1
H2
H3
011
012
013
031
032
033
RRPTR
Payload-pointer and pointer-action bytes
.
The insert H1, H2, and H3 bytes are
inserted into the outgoing terminal data without changing the J1-byte position.
B2
015
035
051
RRB2
Line BIP-8 bit parity
.
The received B2 byte carries the B2 BIP-8 parity. The
parity errors are added to the B2 counter. The recalculated B2 byte is stored
in the insert address.
K1
K2
01E, 05E
01F, 05F
03E
03F
RRAPS
Automatic-protection-switching bytes. The K1 and K2 bytes are debounced
and stored in locations 05E and 05F, respectively. The APS bytes are also
available in the orderwire/APS interface.
D4–D12
028–030
RRLD
Line data-communication channel. The incoming D4 through D12 bytes are
available as a single 576-kbit/s serial HDLC channel on the line-datacom
interface.
E2
019
039
RRE2
Line-orderwire byte. The incoming E2 byte is also available in the orderwire/
APS interface.
Z1
Z2
01A, 05A
01B, 05B
03A
03B
RRZ1
RRZ2
Growth bytes
.
The Z1 and Z2 bytes are debounced and stored in locations 05A
and 05B, respectively.
The insert bytes are multiplexed into the terminal data when the corresponding control bit is set. Otherwise, the incoming bytes are multiplexed
into the terminal data. If used, the microprocessor should initialize the insert locations. This feature is available in pass-through mode only. In
receive-retiming or SPE-only modes, the terminal data has these bytes as an all-zeros pattern.
The E1 byte can be used for AIS transmission. All ones in the E1 byte indicates an AIS condition; all zeros indicates a non-AIS condition. If the
control bit RE2A is set, the TNETS3001 interprets the incoming E1 byte for AIS information. When the control bit RA2E is set, the terminal E1
byte carries AIS information.
P
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