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參數(shù)資料
| 型號： | TNET3001 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SONET STS-1 Overhead Terminator(SONET STS-1附加終端) |
| 中文描述： | SONET的STS - 1的開銷終結(jié)者（SONET的STS - 1的附加終端） |
| 文件頁數(shù)： | 22/49頁 |
| 文件大?。?/td> | 1090K |
| 代理商： | TNET3001 |
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TNETS3001
SONET STS-1 OVERHEAD TERMINATOR
SDNS007B – OCTOBER 1993 – REVISED JUNE 1995
22
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements, C
L
= 15 pF (see Note 4 and Figure 17)
NO.
MIN
MAX
UNIT
μ
s
1
tw(ALEH)
tw(RDL)
tsu(AD)
th(AD)
td(ALE)
td(RD)
td(AD)
td(AD)
td(RD)
td(SEL)
Pulse duration, ALE high
2
Pulse duration, RD low
ns
3
Setup time, AD7–AD0 valid before ALE
↓
ns
4
Hold time, AD7–AD0 valid after ALE
↓
ns
5
Delay time, RD
↑
to ALE
↑
ns
6
Delay time, ALE
↓
to RD
↓
ns
7
Delay time, RD
↓
to AD7–AD0 invalid
ns
8
Delay time, RD
↑
to AD7–AD0
ns
9
Delay time, SEL
↓
to RD
↓
ns
10
Delay time, RD
↑
to SEL
↑
ns
RDY goes low when the address being written to corresponds to a RAM location but remains high during status or control-register access.
NOTE 4: Timing intervals are measured at (VOH–VOL)/2 or (VIH–VIL)/2 as applicable.
operating characteristics, C
L
= 15 pF (see Note 4 and Figure 17)
NO.
MIN
MAX
UNIT
11
tw(RDYL)
td(RDY)
td(RDY)
Pulse duration, RDY low
ns
12
Delay time, AD7–AD0 to RDY
↑
ns
13
Delay time, RD
↓
to RDY
↓
ns
AD7–AD0
(input/output)
ALE
(input)
1
5
6
RD
(input)
A8
(input)
9
SEL
(input)
RDY
(output)
2
3
4
8
10
13
11
VCC (1 – e–t/RC)
(see Note A)
7
Address
12
Data
NOTE A: Open-drain rise time is dependent upon external pullup resistor and load capacitance.
Figure 17. Microprocessor Read-Cycle Timing
P
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