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參數(shù)資料
| 型號： | TNET3001 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SONET STS-1 Overhead Terminator(SONET STS-1附加終端) |
| 中文描述： | SONET的STS - 1的開銷終結(jié)者（SONET的STS - 1的附加終端） |
| 文件頁數(shù)： | 40/49頁 |
| 文件大?。?/td> | 1090K |
| 代理商： | TNET3001 |
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TNETS3001
SONET STS-1 OVERHEAD TERMINATOR
SDNS007B – OCTOBER 1993 – REVISED JUNE 1995
40
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
transmit path-overhead byte RAM locations
SYMBOL
ADDRESS (hex)
CONTROL
BIT
DESCRIPTION
INCOMING
INSERT
J1
180-1BF
180-1BF
TPATH
Path trace. The incoming/outgoing message is stored into/extracted from the
RAM locations in a rotating fashion. There is no specified starting point, but any
incoming J1 byte is written to/read from the next sequential RAM location.
B3
1C0
1C8
TPATH
TRERR
Path BIP-8 parity. The parity errors are added to the B3 counter. The
recalculated B3 byte is stored in the insert address. The recalculated B3 is
XORed with the B3 error mask from location 1D0 before transmission.
C2
1C1
1C9
TPATH
Path-signal label. Normal operation.
G1
1C2
1CA
TPATH
Path status. If TPATH is set, the TNETS3001 sends a FEBE indication in the
upper nibble of the outgoing G1 byte automatically. A path-yellow indication
can be sent by setting bit 3 to one. The path-yellow indication should be sent
2-3 seconds after the following receive alarms are active: RLOS, RLOF,
RLAIS, RLOP and RPAIS; and it should be removed 10–20 seconds after the
receive alarms are cleared.
F2
1C3
1CB
TPATH
Path-user channel. Normal operation.
H4
1C4
1CC
Multiframe indicator. The H4 byte always passes through the TNETS3001
without modification.
Z3
Z4
Z5
1C5
1C6
1C7
1CD
1CE
1CF
TPATH
Path growth. Normal operation.
The insert bytes are multiplexed into the line data stream when the corresponding control bit is set. Otherwise, the incoming bytes are multiplexed
into the line data stream.
If TRERR is set, the error masks are reset after transmission; otherwise, error is transmitted continuously.
transmit performance-monitor locations
§
SYMBOL
ADDRESS
(hex)
BITS
DISABLE
CONDITIONS
DESCRIPTION
B1
146
7–0
TLOS, TLOF
Counts B1 BIP-8 parity errors
B2
147
7–0
TLOS, TLOF, TLAIS
Counts incoming B2 BIP-8 parity errors
INC
7–4
TLOS TLOF TLAIS
TLOS, TLOF, TLAIS,
TLOP, TPAIS
Counts incoming pointer increments
DEC
145
3–0
Counts incoming pointer decrements
B3
1D4
7–0
Counts incoming B3 BIP-8 parity errors
The insert bytes are multiplexed into the line data stream when the corresponding control bit is set. Otherwise, the incoming bytes are multiplexed
into the line data stream.
§All performance monitors saturate at the maximum value and reset to zero on read.
P
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