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參數(shù)資料
| 型號(hào)： | TNET3001 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | SONET STS-1 Overhead Terminator(SONET STS-1附加終端) |
| 中文描述： | SONET的STS - 1的開銷終結(jié)者（SONET的STS - 1的附加終端） |
| 文件頁數(shù)： | 33/49頁 |
| 文件大?。?/td> | 1090K |
| 代理商： | TNET3001 |
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TNETS3001
SONET STS-1 OVERHEAD TERMINATOR
SDNS007B – OCTOBER 1993 – REVISED JUNE 1995
33
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
status register 1 (see Notes 22, 23, and 24)
BIT
SYMBOL
NAME
Rising-edge/both-edges alarms,
new debounced-overhead bytes or
performance-monitor overflow
BIT
SYMBOL
NAME
Microprocessor read from address
0F2 or writing one to bit 7 of
address 0F3
0F2, 0F3
7
INT
Interrupt
0F2, 0F3
6
RTNEW
Receive new
debounced-transport-
overhead byte
Any new debounced value for the
following TOH bytes: C1, F1, K1, K2,
Z1, and Z2
Microprocessor read from
address 0F2 or writing one to
bit 6 of address 0F3
0F2, 0F3
5
RPNEW
Receive new
debounced-path-
overhead byte
Any new debounced value for the
following POH bytes: C2, F2, Z3, Z4,
and Z5
Microprocessor read from
address 0F2 or writing one to
bit 5 of address 0F3
0F2, 0F3,
0F5
4
RPYE
Receive path yellow
Ten consecutive frames of 1 in bit 3
(bit 5 transmission-bit standard) of
the G1 byte
Ten consecutive frames of zero
in the bit 3 (bit 5 transmission-bit
standard) of the G1 byte
0F2, 0F3,
0F5
3
RFERF
Receive FERF
Five consecutive frames of 110 in the
bits 2, 1, 0 (bits 6, 7, 8 transmission-bit
standard) of the K2 byte
Five consecutive frames of 000 or
111 in the bits 2,1,0 (bits 6,7,8
transmission-bit standard) of the
K2 byte
0F2, 0F3,
0F5
2
RAPS
Receive APS bytes
failure
Twelve successive frames with no three
consecutive frames containing identical
APS bytes
Three consecutive frames
containing identical APS bytes
0F2, 0F3,
0F5
1
unused
0F2, 0F3,
0F5
NOTES: 22. The address 0F2 contains latched values of these status bits, which reset on read.
23. The address 0F3 contains latched values of these status bits, but do not reset on read. Write one to individual bit to reset. Write back
read value to reset the entire register.
24. The address 0F5 contains unlatched values of these status bits.
0
unused
P
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