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參數(shù)資料
| 型號： | TNETA1556 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 155.52-Mbit/S Clock-Recovery Device(155.52-MBIT/S時鐘恢復裝置) |
| 中文描述： | 155.52 - Mbit / s的時鐘恢復裝置（155.52 - Mbit / s的時鐘恢復裝置） |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 216K |
| 代理商： | TNETA1556 |
TNETA1556
155.52-MBIT/S CLOCK-RECOVERY DEVICE
SDNS015C – FEBRUARY 1994 – REVISED JUNE 1995
Copyright
1995, Texas Instruments Incorporated
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Recovers a 155.52-MHz Clock Signal From
a 155.52-Mbit/s STS-3/STM-1 NRZ Data
Stream
Accepts ECL or Pseudo-ECL (PECL) Input
Voltage Levels on the Input Data Stream
Provides a Separate Pseudo-ECL-to-True-
ECL Converter for an Additional Data
Signal Requiring Conversion
Requires a Single 5-V Supply
description
The TNETA1556 device recovers an embedded
clock signal from a 155.52-Mbit/s STS-3/STM-1
nonreturn-to-zero (NRZ) data stream using a
frequency/phase-lock loop. This device accepts
either ECL or pseudo-ECL (ECL signals referenced to 5 V instead of GND) input voltage levels. The recovered
clock and data outputs are ECL compatible. The serial data input and recovered clock and data outputs are
differential to provide maximum noise immunity.
The input disable (INDIS) disconnects the incoming serial data stream from the clock-recovery circuitry. When
the INDIS input is high, the data output is forced low and the clock-recovery circuitry maintains the output
frequency present at the time the input was disabled for a specific amount of time. This time is dependent upon
the value of the capacitor in the loop filter.
A pseudo-ECL-to-true-ECL converter is included in the device for those applications where an interface
between the two different voltage levels is required. An example of such an application is an optical transmitter
that requires ECL input voltage levels and a parallel-to-serial converter with ECL-level outputs.
The TNETA1556 requires only a positive 5-V supply (5 V
±
5%) for operation. This device is specified for
operation over a temperature range of –40
°
C to 85
°
C.
functional block diagram
5
4
6
INDIS
DIN
DIN
Clock Recovery
(frequency/
phase-lock loop)
17
18
21
20
DOUT
DOUT
CLK
CLK
PECL-to-ECL
Converter
14
15
13
12
DATAIN
DATAIN
DATAOUT
DATAOUT
2
CPLL
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
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4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
CPLL
GND
DIN
INDIS
DIN
V
CC
GND
TESTOUT
GND
V
CC
DATAOUT
TEST1
TEST2
V
CC
CLK
CLK
GND
DOUT
DOUT
V
CC
DATAIN
DATAIN
DATAOUT
DW PACKAGE
(TOP VIEW)
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
P
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