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參數(shù)資料
| 型號： | TNETA1556 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 155.52-Mbit/S Clock-Recovery Device(155.52-MBIT/S時鐘恢復裝置) |
| 中文描述： | 155.52 - Mbit / s的時鐘恢復裝置（155.52 - Mbit / s的時鐘恢復裝置） |
| 文件頁數(shù)： | 3/10頁 |
| 文件大小： | 216K |
| 代理商： | TNETA1556 |
TNETA1556
155.52-MBIT/S CLOCK-RECOVERY DEVICE
SDNS015C – FEBRUARY 1994 – REVISED JUNE 1995
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
High-level
output voltage
CLK, CLK, DATAOUT,
DATAOUT, DOUT, DOUT
VCC = 4.75 V,
See Notes 2 and 3
–1.02
–0.75
V
VOL
Low-level
output voltage
CLK, CLK, DATAOUT,
DATAOUT, DOUT, DOUT
VCC = 4.75 V,
See Notes 2 and 3
–1.81
–1.58
V
VIK
Input clamp
voltage
INDIS
VCC = 4.75 V,
II = –18 mA
–1.2
V
II
Input current
INDIS
VCC = 5.25 V,
VI = VCC or GND
VI = 4.45 V (PECL)
VI = –0.84 V (ECL)
VI = 3.35 V (PECL)
VI = –1.8 V (ECL)
fi = 155.52 Mbit/s,
±
1
μ
A
IIH
High-level
High level
input current
DIN, DIN,
DATAIN, DATAIN
VCC= 5 25 V
VCC = 5.25 V,
50
μ
A
IIL
Low-level
Low level
input current
DIN, DIN,
DATAIN, DATAIN
VCC= 5 25 V
VCC = 5.25 V,
50
μ
A
ICC
Supply current
VCC = 5.25 V,
Outputs open
71
100
mA
VCC = 5.25 V,
See Note 4
fi = 155.52 Mbit/s,
112
150
NOTES:
2. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for
logic-level voltages only.
3. These outputs are terminated through a 50-
resistor to –2 V.
4. DOUT, DOUT, CLK, CLK, DATAOUT, and DATAOUT are terminated with a 50-
resistor to –2 V.
operating characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
TEST CONDITIONS
CPLL = 330 pF
MIN
TYP
MAX
UNIT
Acquisition time
See Note 5
1
ms
CPLL = 0.1
μ
F
3
Deviation of clock sampling point, tcsp
RMS jitter, recovered clock
–800
800
4
°
ps
See Note 6
1.5
°
°
RMS
Mb/s
Input data rate
155.52
Duty cycle, recovered clock
See Note 3
45%
55%
Maximum number of consecutive bits (1 or 0) in input data stream
3. These outputs are terminated through a 50-
resistor to –2 V.
5. Acquisition time is the time required to achieve a valid clock output while applying a 27 –1 pseudo-random bit sequence.
6. RMS jitter is measured with a 231 –1 pseudo-random bit sequence.
7. This measurement is made with a 213 –1 pseudo-random bit sequence with string substitution.
See Note 7
100
450
NOTES:
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
±
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
MAX
UNIT
tPLH
tPHL
DATAIN or DATAIN
DATAOUT or DATAOUT
1.5
1.5
4.5
4.5
ns
P
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